riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Guarantee probe forward progress during LR storm

Browse Source
This commit is contained in:
Andrew Waterman
2017-04-14 01:09:13 -07:00
committed by Andrew Waterman
parent 71eaed7d60
commit 7871ec82c4
3 changed files with 7 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/main/scala/rocket/HellaCache.scala
View File

@ -58,6 +58,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParamet
def encDataBits = code.width(coreDataBits)
def encRowBits = encDataBits*rowWords
def lrscCycles = 32 // ISA requires 16-insn LRSC sequences to succeed
def lrscBackoff = 3 // disallow LRSC reacquisition briefly
def nIOMSHRs = cacheParams.nMMIOs
def maxUncachedInFlight = cacheParams.nMMIOs
def dataScratchpadSize = cacheParams.dataScratchpadBytes