riscv/rocket-chip
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Merge pull request #370 from ucb-bar/move_clint_and_plic

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clint & plic: Move the default addresses
This commit is contained in:
mwachs5
2016-10-01 16:18:54 -07:00
committed by GitHub
parent 9a381e88d1 28eba9b5ac
commit 784f0cf0b6
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/rocketchip/Utils.scala
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@@ -56,7 +56,7 @@ object GenerateGlobalAddrMap {
lazy val cBusIOAddrMap: AddrMap = { lazy val cBusIOAddrMap: AddrMap = {
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]() val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX))) entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW))) entries += AddrMapEntry("plic", MemRange(0x0C000000, 0x4000000, MemAttr(AddrMapProt.RW)))
if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
require(p(NTiles) == 1) // TODO relax this require(p(NTiles) == 1) // TODO relax this
require(p(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM require(p(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM

2
src/main/scala/uncore/devices/Prci.scala
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@@ -19,7 +19,7 @@ class CoreplexLocalInterrupts extends Bundle {
val msip = Bool() val msip = Bool()
} }
case class CoreplexLocalInterrupterConfig(beatBytes: Int, address: BigInt = 0x44000000) { case class CoreplexLocalInterrupterConfig(beatBytes: Int, address: BigInt = 0x02000000) {
def msipOffset(hart: Int) = hart * msipBytes def msipOffset(hart: Int) = hart * msipBytes
def msipAddress(hart: Int) = address + msipOffset(hart) def msipAddress(hart: Int) = address + msipOffset(hart)
def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes