From 28eba9b5ac100265c3d6a62db7770f7151e820d4 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Sat, 1 Oct 2016 15:46:55 -0700 Subject: [PATCH] clint/plic: Move the default addresses --- src/main/scala/rocketchip/Utils.scala | 2 +- src/main/scala/uncore/devices/Prci.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala index 159b0c52..88fb8436 100644 --- a/src/main/scala/rocketchip/Utils.scala +++ b/src/main/scala/rocketchip/Utils.scala @@ -56,7 +56,7 @@ object GenerateGlobalAddrMap { lazy val cBusIOAddrMap: AddrMap = { val entries = collection.mutable.ArrayBuffer[AddrMapEntry]() entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX))) - entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW))) + entries += AddrMapEntry("plic", MemRange(0x0C000000, 0x4000000, MemAttr(AddrMapProt.RW))) if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles require(p(NTiles) == 1) // TODO relax this require(p(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM diff --git a/src/main/scala/uncore/devices/Prci.scala b/src/main/scala/uncore/devices/Prci.scala index 185458db..519f9f43 100644 --- a/src/main/scala/uncore/devices/Prci.scala +++ b/src/main/scala/uncore/devices/Prci.scala @@ -19,7 +19,7 @@ class CoreplexLocalInterrupts extends Bundle { val msip = Bool() } -case class CoreplexLocalInterrupterConfig(beatBytes: Int, address: BigInt = 0x44000000) { +case class CoreplexLocalInterrupterConfig(beatBytes: Int, address: BigInt = 0x02000000) { def msipOffset(hart: Int) = hart * msipBytes def msipAddress(hart: Int) = address + msipOffset(hart) def timecmpOffset(hart: Int) = 0x4000 + hart * timecmpBytes