riscv/rocket-chip
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fix Chisel3 compat issue in SimpleHellaCacheIF

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This commit is contained in:
Howard Mao 2016-01-14 22:42:44 -08:00
parent 120361226d
commit 77e068c153
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -1120,8 +1120,8 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
// stash d$ request in stage 1 if nacked (newer request) // stash d$ request in stage 1 if nacked (newer request)
replayq2.io.enq.valid := s2_req_fire && s3_nack replayq2.io.enq.valid := s2_req_fire && s3_nack
replayq2.io.enq.bits.data := io.cache.resp.bits.store_data
replayq2.io.enq.bits <> io.cache.resp.bits replayq2.io.enq.bits <> io.cache.resp.bits
replayq2.io.enq.bits.data := io.cache.resp.bits.store_data
replayq2.io.deq.ready := Bool(false) replayq2.io.deq.ready := Bool(false)
when (s2_nack) { when (s2_nack) {