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plic: comment tidying

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Megan Wachs 2017-06-30 12:51:09 -07:00
parent 3da26b0aa8
commit 76f8de75e3
1 changed files with 1 additions and 1 deletions
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src/main/scala/uncore/devices/Plic.scala
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@ -198,7 +198,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
// This code expolits the fact that, practically, only one claim/complete register // This code expolits the fact that, practically, only one claim/complete register
// can be written at a time. We check for this because if the address map // can be written at a time. We check for this because if the address map
// were to change, it may no longer be true. // were to change, it may no longer be true.
// (Note -- PLIC doesn't care which hart writes the register) // Note -- PLIC doesn't care which hart writes the register.
val completer = Wire(Vec(nHarts, Bool())) val completer = Wire(Vec(nHarts, Bool()))
assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot
val completerDev = Wire(UInt(width = log2Up(nDevices + 1))) val completerDev = Wire(UInt(width = log2Up(nDevices + 1)))