From 76f8de75e35a805aba1bf877766095b2b6bc190e Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 30 Jun 2017 12:51:09 -0700 Subject: [PATCH] plic: comment tidying --- src/main/scala/uncore/devices/Plic.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala index 7509cd3e..d6fff5dd 100644 --- a/src/main/scala/uncore/devices/Plic.scala +++ b/src/main/scala/uncore/devices/Plic.scala @@ -198,7 +198,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule // This code expolits the fact that, practically, only one claim/complete register // can be written at a time. We check for this because if the address map // were to change, it may no longer be true. - // (Note -- PLIC doesn't care which hart writes the register) + // Note -- PLIC doesn't care which hart writes the register. val completer = Wire(Vec(nHarts, Bool())) assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot val completerDev = Wire(UInt(width = log2Up(nDevices + 1)))