riscv/rocket-chip
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crossings: stop using deprecated APIs in tests

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This commit is contained in:
Wesley W. Terpstra 2017-10-25 17:47:09 -07:00
parent 380cc6f03b
commit 76df1397e0
3 changed files with 11 additions and 35 deletions
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16
src/main/scala/amba/axi4/AsyncCrossing.scala
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@ -8,6 +8,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.coreplex.{CrossingWrapper, AsynchronousCrossing}
class AXI4AsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
@ -89,28 +90,21 @@ import freechips.rocketchip.unittest._
class AXI4RAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
val model = LazyModule(new TLRAMModel("AsyncCrossing"))
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
val fuzz = LazyModule(new TLFuzzer(txns))
val toaxi = LazyModule(new TLToAXI4)
val cross = LazyModule(new AXI4AsyncCrossing)
val island = LazyModule(new CrossingWrapper(AsynchronousCrossing(8)))
val ram = island { LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) }
model.node := fuzz.node
toaxi.node := model.node
cross.node := toaxi.node
ram.node := cross.node
ram.node := island.crossAXI4In := toaxi.node
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
// Shove the RAM into another clock domain
val clocks = Module(new Pow2ClockDivider(2))
ram.module.clock := clocks.io.clock_out
// ... and safely cross AXI42 into it
cross.module.io.in_clock := clock
cross.module.io.in_reset := reset
cross.module.io.out_clock := clocks.io.clock_out
cross.module.io.out_reset := reset
island.module.clock := clocks.io.clock_out
}
}

16
src/main/scala/tilelink/AsyncCrossing.scala
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@ -7,6 +7,7 @@ import chisel3.internal.sourceinfo.SourceInfo
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.coreplex.{CrossingWrapper, AsynchronousCrossing}
class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
@ -113,26 +114,19 @@ import freechips.rocketchip.unittest._
class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
val model = LazyModule(new TLRAMModel("AsyncCrossing"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
val fuzz = LazyModule(new TLFuzzer(txns))
val cross = LazyModule(new TLAsyncCrossing)
val island = LazyModule(new CrossingWrapper(AsynchronousCrossing(8)))
val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) }
model.node := fuzz.node
cross.node := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node))
ram.node := cross.node
ram.node := island.crossTLIn := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node))
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
// Shove the RAM into another clock domain
val clocks = Module(new Pow2ClockDivider(2))
ram.module.clock := clocks.io.clock_out
// ... and safely cross TL2 into it
cross.module.io.in_clock := clock
cross.module.io.in_reset := reset
cross.module.io.out_clock := clocks.io.clock_out
cross.module.io.out_reset := reset
island.module.clock := clocks.io.clock_out
}
}

14
src/main/scala/tilelink/Fuzzer.scala
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@ -233,28 +233,16 @@ class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
val xbar = LazyModule(new TLXbar)
val xbar2= LazyModule(new TLXbar)
val fuzz = LazyModule(new TLFuzzer(txns))
val cross = LazyModule(new TLAsyncCrossing)
model.node := fuzz.node
xbar2.node := TLAtomicAutomata()(model.node)
ram2.node := TLFragmenter(16, 256)(xbar2.node)
xbar.node := TLWidthWidget(16)(TLHintHandler()(xbar2.node))
cross.node := TLFragmenter(4, 256)(TLBuffer()(xbar.node))
ram.node := cross.node
ram.node := TLFragmenter(4, 256)(TLBuffer()(xbar.node))
gpio.node := TLFragmenter(4, 32)(TLBuffer()(xbar.node))
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
// Shove the RAM into another clock domain
val clocks = Module(new Pow2ClockDivider(2))
ram.module.clock := clocks.io.clock_out
// ... and safely cross TL2 into it
cross.module.io.in_clock := clock
cross.module.io.in_reset := reset
cross.module.io.out_clock := clocks.io.clock_out
cross.module.io.out_reset := reset
}
}