136 lines
4.3 KiB
Scala
136 lines
4.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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import freechips.rocketchip.coreplex.{CrossingWrapper, AsynchronousCrossing}
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class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val node = TLAsyncSourceNode(sync)
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val sink_reset_n = out.a.sink_reset_n
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val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
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val depth = edgeOut.manager.depth
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out.a <> ToAsyncBundle(in.a, depth, sync)
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in.d <> FromAsyncBundle(out.d, sync)
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if (bce) {
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in.b <> FromAsyncBundle(out.b, sync)
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out.c <> ToAsyncBundle(in.c, depth, sync)
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out.e <> ToAsyncBundle(in.e, depth, sync)
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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out.b.ridx := UInt(0)
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out.c.widx := UInt(0)
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out.e.widx := UInt(0)
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}
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}
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}
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}
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class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val node = TLAsyncSinkNode(depth, sync)
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val source_reset_n = in.a.source_reset_n
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val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe
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out.a <> FromAsyncBundle(in.a, sync)
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in.d <> ToAsyncBundle(out.d, depth, sync)
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if (bce) {
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in.b <> ToAsyncBundle(out.b, depth, sync)
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out.c <> FromAsyncBundle(in.c, sync)
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out.e <> FromAsyncBundle(in.e, sync)
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} else {
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in.b.widx := UInt(0)
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in.c.ridx := UInt(0)
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in.e.ridx := UInt(0)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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}
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}
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object TLAsyncCrossingSource
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{
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// applied to the TL source node; y.node := TLAsyncCrossingSource()(x.node)
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def apply(sync: Int = 3)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLAsyncOutwardNode = {
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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source.node :=? x
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source.node
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}
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}
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object TLAsyncCrossingSink
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{
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// applied to the TL source node; y.node := TLAsyncCrossingSink()(x.node)
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def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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sink.node :=? x
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sink.node
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}
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}
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class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val node = NodeHandle(source.node, sink.node)
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sink.node := source.node
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val in_clock = Clock(INPUT)
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val in_reset = Bool(INPUT)
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val out_clock = Clock(INPUT)
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val out_reset = Bool(INPUT)
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})
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source.module.clock := io.in_clock
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source.module.reset := io.in_reset
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sink.module.clock := io.out_clock
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sink.module.reset := io.out_reset
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}
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}
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/** Synthesizeable unit tests */
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import freechips.rocketchip.unittest._
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class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
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val model = LazyModule(new TLRAMModel("AsyncCrossing"))
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val fuzz = LazyModule(new TLFuzzer(txns))
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val island = LazyModule(new CrossingWrapper(AsynchronousCrossing(8)))
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val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) }
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model.node := fuzz.node
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ram.node := island.crossTLIn := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node))
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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// Shove the RAM into another clock domain
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val clocks = Module(new Pow2ClockDivider(2))
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island.module.clock := clocks.io.clock_out
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}
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}
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class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
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io.finished := Module(LazyModule(new TLRAMAsyncCrossing(txns)).module).io.finished
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}
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