allow icache to configure which side of the way mux gets buffered
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369ee74a2c
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7690de07e1
@ -46,14 +46,15 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_btb_resp_bits = Reg(btb.io.resp.bits)
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val s2_xcpt_if = Reg(init=Bool(false))
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val icbuf = Module(new Queue(new ICacheResp, 1, pipe=true))
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val s2_resp_valid = Wire(init=Bool(false))
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val s2_resp_data = Wire(UInt(width = rowBits))
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val msb = vaddrBits-1
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val lsb = log2Up(fetchWidth*coreInstBytes)
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val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
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val ntpc_0 = s1_pc + UInt(coreInstBytes*fetchWidth)
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val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
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val icmiss = s2_valid && !icbuf.io.deq.valid
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val icmiss = s2_valid && !s2_resp_valid
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val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
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val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
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val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((ntpc & rowBytes) === (s1_pc & rowBytes))
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@ -101,17 +102,29 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
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icmiss || io.ptw.invalidate
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icache.io.resp.ready := !stall && !s1_same_block
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icbuf.io.deq.valid)
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io.cpu.resp.valid := s2_valid && (s2_xcpt_if || s2_resp_valid)
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io.cpu.resp.bits.pc := s2_pc
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io.cpu.npc := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
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// if the ways are buffered, we don't need to buffer again
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if (p(ICacheBufferWays)) {
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icache.io.resp.ready := !stall && !s1_same_block
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s2_resp_valid := icache.io.resp.valid
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s2_resp_data := icache.io.resp.bits.datablock
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} else {
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val icbuf = Module(new Queue(new ICacheResp, 1, pipe=true))
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icbuf.io.enq <> icache.io.resp
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icbuf.io.deq.ready := !stall && !s1_same_block
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s2_resp_valid := icbuf.io.deq.valid
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s2_resp_data := icbuf.io.deq.bits.datablock
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}
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require(fetchWidth * coreInstBytes <= rowBytes)
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val fetch_data =
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if (fetchWidth * coreInstBytes == rowBytes) icbuf.io.deq.bits.datablock
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else icbuf.io.deq.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(fetchWidth*coreInstBytes)) << log2Up(fetchWidth*coreInstBits))
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if (fetchWidth * coreInstBytes == rowBytes) s2_resp_data
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else s2_resp_data >> (s2_pc(log2Up(rowBytes)-1,log2Up(fetchWidth*coreInstBytes)) << log2Up(fetchWidth*coreInstBits))
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for (i <- 0 until fetchWidth) {
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io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
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@ -5,6 +5,8 @@ import uncore._
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import Util._
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import cde.{Parameters, Field}
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case object ICacheBufferWays extends Field[Boolean]
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trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
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val outerDataBeats = p(TLKey(p(TLId))).dataBeats
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val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
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@ -124,10 +126,18 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
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s1_dout(i) := 0
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when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s1_dout(i) := s1_rdata }
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}
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io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
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// output signals
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if (p(ICacheBufferWays)) {
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val s2_hit = RegEnable(s1_hit, !stall)
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val s2_tag_hit = RegEnable(s1_tag_hit, !stall)
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val s2_dout = RegEnable(s1_dout, !stall)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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io.resp.valid := s2_hit
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} else {
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io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
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io.resp.valid := s1_hit
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}
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io.mem.acquire.valid := (state === s_request)
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io.mem.acquire.bits := GetBlock(addr_block = refill_addr >> blockOffBits)
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