riscv/rocket-chip
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allow icache to configure which side of the way mux gets buffered

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This commit is contained in:
Howard Mao
2015-12-02 17:17:49 -08:00
parent 369ee74a2c
commit 7690de07e1
2 changed files with 32 additions and 9 deletions
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14
rocket/src/main/scala/icache.scala
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@@ -5,6 +5,8 @@ import uncore._
import Util._
import cde.{Parameters, Field}
case object ICacheBufferWays extends Field[Boolean]
trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
val outerDataBeats = p(TLKey(p(TLId))).dataBeats
val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
@@ -124,10 +126,18 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
s1_dout(i) := 0
when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s1_dout(i) := s1_rdata }
}
io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
// output signals
io.resp.valid := s1_hit
if (p(ICacheBufferWays)) {
val s2_hit = RegEnable(s1_hit, !stall)
val s2_tag_hit = RegEnable(s1_tag_hit, !stall)
val s2_dout = RegEnable(s1_dout, !stall)
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
io.resp.valid := s2_hit
} else {
io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
io.resp.valid := s1_hit
}
io.mem.acquire.valid := (state === s_request)
io.mem.acquire.bits := GetBlock(addr_block = refill_addr >> blockOffBits)