riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Stall on D$ lockups less conservatively

Browse Source
This commit is contained in:
Andrew Waterman
2016-05-21 16:56:49 -07:00
parent a3061047e3
commit 765b90f6a4
1 changed files with 4 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
rocket/src/main/scala/rocket.scala
View File

@@ -483,10 +483,13 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
id_csr_en && !io.fpu.fcsr_rdy || checkHazards(fp_hazard_targets, fp_sboard.read _)
} else Bool(false)
val dcache_blocked = Reg(Bool())
dcache_blocked := !io.dmem.req.ready && (io.dmem.req.valid || dcache_blocked)
val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
id_ctrl.fp && id_stall_fpu ||
id_ctrl.mem && Reg(next = !io.dmem.req.ready) ||
id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses
Bool(usingRoCC) && wb_reg_rocc_pending && id_ctrl.rocc && !io.rocc.cmd.ready ||
id_do_fence ||
csr.io.csr_stall