regmapper: detect improper reset sequencing in RegisterCrossing
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@ -35,6 +35,15 @@ class BusyRegisterCrossing extends Module {
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io.master_response_valid := (bypass || io.crossing_request_ready) && busy
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io.master_response_valid := (bypass || io.crossing_request_ready) && busy
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}
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}
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class RegisterCrossingAssertion extends Module {
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val io = new Bundle {
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val master_bypass = Bool(INPUT)
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val slave_reset = Bool(INPUT)
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}
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assert (io.master_bypass || !io.slave_reset)
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}
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// RegField should support connecting to one of these
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// RegField should support connecting to one of these
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class RegisterWriteIO[T <: Data](gen: T) extends Bundle {
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class RegisterWriteIO[T <: Data](gen: T) extends Bundle {
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val request = Decoupled(gen).flip
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val request = Decoupled(gen).flip
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@ -101,6 +110,12 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
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crossing.io.deq.ready := Bool(true)
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crossing.io.deq.ready := Bool(true)
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io.slave_valid := crossing.io.deq.valid
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io.slave_valid := crossing.io.deq.valid
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io.slave_register := crossing.io.deq.bits
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io.slave_register := crossing.io.deq.bits
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val assertion = Module(new RegisterCrossingAssertion)
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assertion.clock := io.master_clock
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assertion.reset := io.master_reset
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assertion.io.master_bypass := io.master_bypass
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assertion.io.slave_reset := io.slave_reset
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}
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}
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// RegField should support connecting to one of these
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// RegField should support connecting to one of these
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@ -147,6 +162,12 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
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crossing.io.enq.valid := Bool(true)
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crossing.io.enq.valid := Bool(true)
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crossing.io.enq.bits := io.slave_register
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crossing.io.enq.bits := io.slave_register
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val assertion = Module(new RegisterCrossingAssertion)
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assertion.clock := io.master_clock
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assertion.reset := io.master_reset
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assertion.io.master_bypass := io.master_bypass
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assertion.io.slave_reset := io.slave_reset
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}
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}
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/** Wrapper to create an
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/** Wrapper to create an
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