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Merge remote-tracking branch 'origin/master' into jchang_test

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This commit is contained in:
Jacob Chang
2016-12-09 16:56:49 -08:00
parent 4c3083c181 09afbbafdb
commit 762afcd54a
67 changed files with 950 additions and 270 deletions
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9
src/main/scala/uncore/tilelink2/AtomicAutomata.scala
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@ -4,12 +4,13 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import scala.math.{min,max}
// Ensures that all downstream RW managers support Atomic operationss.
// If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream.
class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true) extends LazyModule
class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require (concurrency >= 1)
@ -278,7 +279,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
object TLAtomicAutomata
{
// applied to the TL source node; y.node := TLAtomicAutomata(x.node)
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
atomics.node := x
atomics.node
@ -290,7 +291,7 @@ import unittest._
//TODO ensure handler will pass through operations to clients that can handle them themselves
class TLRAMAtomicAutomata() extends LazyModule {
class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
@ -303,6 +304,6 @@ class TLRAMAtomicAutomata() extends LazyModule {
}
}
class TLRAMAtomicAutomataTest extends UnitTest(timeout = 500000) {
class TLRAMAtomicAutomataTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new TLRAMAtomicAutomata).module).io.finished
}

25
src/main/scala/uncore/tilelink2/Broadcast.scala
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@ -3,10 +3,11 @@
package uncore.tilelink2
import Chisel._
import config._
import diplomacy._
import scala.math.{min,max}
class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false) extends LazyModule
class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false)(implicit p: Parameters) extends LazyModule
{
require (lineBytes > 0 && isPow2(lineBytes))
require (numTrackers > 0)
@ -87,6 +88,8 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
val d_normal = Wire(in.d)
val d_trackerOH = Vec(trackers.map { t => !t.idle && t.source === d_normal.bits.source }).asUInt
assert (!out.d.valid || !d_drop || out.d.bits.opcode === TLMessages.AccessAck)
out.d.ready := d_normal.ready || d_drop
d_normal.valid := out.d.valid && !d_drop
d_normal.bits := out.d.bits // truncates source
@ -102,6 +105,7 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
val d_last = edgeIn.last(d_normal)
(trackers zip d_trackerOH.toBools) foreach { case (tracker, select) =>
tracker.d_last := select && d_normal.fire() && d_response && d_last
tracker.probedack := select && out.d.fire() && d_drop
}
// Incoming C can be:
@ -114,12 +118,12 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
val c_probeackdata = in.c.bits.opcode === TLMessages.ProbeAckData
val c_releasedata = in.c.bits.opcode === TLMessages.ReleaseData
val c_release = in.c.bits.opcode === TLMessages.Release
val c_trackerOH = trackers.map { t => t.line === (in.c.bits.address >> lineShift) }
val c_trackerSrc = Mux1H(c_trackerOH, trackers.map { _.source })
// Decrement the tracker's outstanding probe counter
val c_decrement = in.c.fire() && (c_probeack || c_probeackdata)
val c_last = edgeIn.last(in.c)
trackers foreach { tracker =>
tracker.probeack := c_decrement && c_last && tracker.line === (in.c.bits.address >> lineShift)
(trackers zip c_trackerOH) foreach { case (tracker, select) =>
tracker.probenack := in.c.fire() && c_probeack && select
}
val releaseack = Wire(in.d)
@ -131,8 +135,9 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
releaseack.bits := edgeIn.ReleaseAck(in.c.bits.address, UInt(0), in.c.bits.source, in.c.bits.size)
val put_what = Mux(c_releasedata, TRANSFORM_B, DROP)
val put_who = Mux(c_releasedata, in.c.bits.source, c_trackerSrc)
putfull.valid := in.c.valid && (c_probeackdata || c_releasedata)
putfull.bits := edgeOut.Put(Cat(put_what, in.c.bits.source), in.c.bits.address, in.c.bits.size, in.c.bits.data)._2
putfull.bits := edgeOut.Put(Cat(put_what, put_who), in.c.bits.address, in.c.bits.size, in.c.bits.data)._2
// Combine ReleaseAck or the modified D
TLArbiter.lowest(edgeOut, in.d, releaseack, d_normal)
@ -207,7 +212,8 @@ class TLBroadcastTracker(id: Int, lineBytes: Int, probeCountBits: Int, bufferles
val in_a = Decoupled(new TLBundleA(edgeIn.bundle)).flip
val out_a = Decoupled(new TLBundleA(edgeOut.bundle))
val probe = UInt(INPUT, width = probeCountBits)
val probeack = Bool(INPUT)
val probenack = Bool(INPUT)
val probedack = Bool(INPUT)
val d_last = Bool(INPUT)
val e_last = Bool(INPUT)
val source = UInt(OUTPUT) // the source awaiting D response
@ -246,9 +252,10 @@ class TLBroadcastTracker(id: Int, lineBytes: Int, probeCountBits: Int, bufferles
assert (!idle)
idle := Bool(true)
}
when (io.probeack) {
when (io.probenack || io.probedack) {
assert (count > UInt(0))
count := count - UInt(1)
count := count - Mux(io.probenack && io.probedack, UInt(2), UInt(1))
}
io.idle := idle

15
src/main/scala/uncore/tilelink2/Buffer.scala
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@ -4,11 +4,12 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import scala.math.{min,max}
// pipe is only used if a queue has depth = 1
class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe: Boolean = true) extends LazyModule
class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require (a >= 0)
require (b >= 0)
@ -49,12 +50,12 @@ class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe:
object TLBuffer
{
// applied to the TL source node; y.node := TLBuffer(x.node)
def apply() (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(2)(x)
def apply(entries: Int) (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(entries, true)(x)
def apply(entries: Int, pipe: Boolean) (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(entries, entries, pipe)(x)
def apply(ace: Int, bd: Int) (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, true)(x)
def apply(ace: Int, bd: Int, pipe: Boolean)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace, pipe)(x)
def apply(a: Int, b: Int, c: Int, d: Int, e: Int, pipe: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(2)(x)
def apply(entries: Int) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(entries, true)(x)
def apply(entries: Int, pipe: Boolean) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(entries, entries, pipe)(x)
def apply(ace: Int, bd: Int) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, true)(x)
def apply(ace: Int, bd: Int, pipe: Boolean)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace, pipe)(x)
def apply(a: Int, b: Int, c: Int, d: Int, e: Int, pipe: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val buffer = LazyModule(new TLBuffer(a, b, c, d, e, pipe))
buffer.node := x
buffer.node

15
src/main/scala/uncore/tilelink2/Crossing.scala
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@ -4,10 +4,11 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import util._
class TLAsyncCrossingSource(sync: Int = 3) extends LazyModule
class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = TLAsyncSourceNode()
@ -41,7 +42,7 @@ class TLAsyncCrossingSource(sync: Int = 3) extends LazyModule
}
}
class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3) extends LazyModule
class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = TLAsyncSinkNode(depth)
@ -77,7 +78,7 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3) extends LazyModule
object TLAsyncCrossingSource
{
// applied to the TL source node; y.node := TLAsyncCrossingSource()(x.node)
def apply(sync: Int = 3)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLAsyncOutwardNode = {
def apply(sync: Int = 3)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLAsyncOutwardNode = {
val source = LazyModule(new TLAsyncCrossingSource(sync))
source.node := x
source.node
@ -87,14 +88,14 @@ object TLAsyncCrossingSource
object TLAsyncCrossingSink
{
// applied to the TL source node; y.node := TLAsyncCrossingSink()(x.node)
def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
sink.node := x
sink.node
}
}
class TLAsyncCrossing(depth: Int = 8, sync: Int = 3) extends LazyModule
class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val nodeIn = TLInputNode()
val nodeOut = TLOutputNode()
@ -136,7 +137,7 @@ class TLAsyncCrossing(depth: Int = 8, sync: Int = 3) extends LazyModule
/** Synthesizeable unit tests */
import unittest._
class TLRAMCrossing extends LazyModule {
class TLRAMCrossing(implicit p: Parameters) extends LazyModule {
val model = LazyModule(new TLRAMModel)
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
val fuzz = LazyModule(new TLFuzzer(5000))
@ -167,6 +168,6 @@ class TLRAMCrossing extends LazyModule {
}
}
class TLRAMCrossingTest extends UnitTest(timeout = 500000) {
class TLRAMCrossingTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new TLRAMCrossing).module).io.finished
}

7
src/main/scala/uncore/tilelink2/Example.scala
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@ -3,6 +3,7 @@
package uncore.tilelink2
import Chisel._
import config._
import regmapper._
case class ExampleParams(num: Int, address: BigInt)
@ -33,6 +34,6 @@ trait ExampleModule extends HasRegMap
}
// Create a concrete TL2 version of the abstract Example slave
class TLExample(p: ExampleParams) extends TLRegisterRouter(p.address, 4)(
new TLRegBundle(p, _) with ExampleBundle)(
new TLRegModule(p, _, _) with ExampleModule)
class TLExample(params: ExampleParams)(implicit p: Parameters) extends TLRegisterRouter(params.address, 4)(
new TLRegBundle(params, _) with ExampleBundle)(
new TLRegModule(params, _, _) with ExampleModule)

5
src/main/scala/uncore/tilelink2/Filter.scala
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@ -4,10 +4,11 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import scala.math.{min,max}
class TLFilter(select: AddressSet) extends LazyModule
class TLFilter(select: AddressSet)(implicit p: Parameters) extends LazyModule
{
val node = TLAdapterNode(
clientFn = { case Seq(cp) => cp },
@ -44,7 +45,7 @@ class TLFilter(select: AddressSet) extends LazyModule
object TLFilter
{
// applied to the TL source node; y.node := TLBuffer(x.node)
def apply(select: AddressSet)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
def apply(select: AddressSet)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val filter = LazyModule(new TLFilter(select))
filter.node := x
filter.node

9
src/main/scala/uncore/tilelink2/Fragmenter.scala
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@ -4,6 +4,7 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import scala.math.{min,max}
@ -13,7 +14,7 @@ import scala.math.{min,max}
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false)(implicit p: Parameters) extends LazyModule
{
require (isPow2 (maxSize))
require (isPow2 (minSize))
@ -253,7 +254,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
object TLFragmenter
{
// applied to the TL source node; y.node := TLFragmenter(x.node, 256, 4)
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin))
fragmenter.node := x
fragmenter.node
@ -263,7 +264,7 @@ object TLFragmenter
/** Synthesizeable unit tests */
import unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int) extends LazyModule {
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
@ -276,6 +277,6 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int) extends LazyModule {
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int) extends UnitTest(timeout = 500000) {
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize)).module).io.finished
}

7
src/main/scala/uncore/tilelink2/Fuzzer.scala
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@ -3,6 +3,7 @@
package uncore.tilelink2
import Chisel._
import config._
import diplomacy._
class IDMapGenerator(numIds: Int) extends Module {
@ -85,7 +86,7 @@ class TLFuzzer(
(wide: Int, increment: Bool, abs_values: Int) =>
LFSRNoiseMaker(wide=wide, increment=increment)
}
) extends LazyModule
)(implicit p: Parameters) extends LazyModule
{
val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight)))
@ -213,7 +214,7 @@ class TLFuzzer(
/** Synthesizeable integration test */
import unittest._
class TLFuzzRAM extends LazyModule
class TLFuzzRAM()(implicit p: Parameters) extends LazyModule
{
val model = LazyModule(new TLRAMModel("TLFuzzRAM"))
val ram = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
@ -253,7 +254,7 @@ class TLFuzzRAM extends LazyModule
}
}
class TLFuzzRAMTest extends UnitTest(500000) {
class TLFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) {
val dut = Module(LazyModule(new TLFuzzRAM).module)
io.finished := dut.io.finished
}

9
src/main/scala/uncore/tilelink2/HintHandler.scala
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@ -5,10 +5,11 @@ package uncore.tilelink2
import scala.math.min
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
// Acks Hints for managers that don't support them or Acks all Hints if !passthrough
class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends LazyModule
class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
{
val node = TLAdapterNode(
clientFn = { case Seq(c) => if (!supportClients) c else c.copy(minLatency = min(1, c.minLatency), clients = c.clients .map(_.copy(supportsHint = TransferSizes(1, c.maxTransfer)))) },
@ -100,7 +101,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
object TLHintHandler
{
// applied to the TL source node; y.node := TLHintHandler(x.node)
def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
hints.node := x
hints.node
@ -112,7 +113,7 @@ import unittest._
//TODO ensure handler will pass through hints to clients that can handle them themselves
class TLRAMHintHandler() extends LazyModule {
class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
@ -125,6 +126,6 @@ class TLRAMHintHandler() extends LazyModule {
}
}
class TLRAMHintHandlerTest extends UnitTest(timeout = 500000) {
class TLRAMHintHandlerTest()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new TLRAMHintHandler).module).io.finished
}

7
src/main/scala/uncore/tilelink2/IntNodes.scala
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@ -4,6 +4,7 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import scala.collection.mutable.ListBuffer
import scala.math.max
@ -65,7 +66,7 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
override def labelI(ei: IntEdge) = ei.source.sources.map(_.range.size).sum.toString
override def labelO(eo: IntEdge) = eo.source.sources.map(_.range.size).sum.toString
def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
(None, () => {
// Cannot use bulk connect, because the widths could differ
(bo zip bi) foreach { case (o, i) => i := o }
@ -100,7 +101,7 @@ case class IntBlindInputNode(num: Int) extends BlindInputNode(IntImp)(IntSourceP
case class IntInternalOutputNode() extends InternalOutputNode(IntImp)(IntSinkPortParameters(Seq(IntSinkParameters())))
case class IntInternalInputNode(num: Int) extends InternalInputNode(IntImp)(IntSourcePortParameters(Seq(IntSourceParameters(num))))
class IntXbar extends LazyModule
class IntXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode(
numSourcePorts = 0 to 128,
@ -123,7 +124,7 @@ class IntXbar extends LazyModule
}
}
class IntXing extends LazyModule
class IntXing()(implicit p: Parameters) extends LazyModule
{
val intnode = IntIdentityNode()

5
src/main/scala/uncore/tilelink2/Isolation.scala
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@ -4,11 +4,12 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import util.AsyncBundle
// READ the comments in the TLIsolation object before you instantiate this module
class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt) extends LazyModule
class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implicit p: Parameters) extends LazyModule
{
val node = TLAsyncIdentityNode()
@ -76,7 +77,7 @@ object TLIsolation
// fOut is applied to data flowing from client to manager
// fIn is applied to data flowing from manager to client
// **** WARNING: the isolation functions must bring the values to 0 ****
def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = {
def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = {
val iso = LazyModule(new TLIsolation(fOut, fIn))
iso.node := x
(iso.node, () => (iso.module.io.iso_out, iso.module.io.iso_in))

10
src/main/scala/uncore/tilelink2/Legacy.scala
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@ -8,19 +8,15 @@ import config._
import uncore.tilelink._
import uncore.constants._
// Instantiate 'val p' before HasTileLinkParameters tries to use it
abstract class LegacyLazyModuleImp(module: LazyModule)(implicit val p: Parameters)
extends LazyModuleImp(module) with HasTileLinkParameters
class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkParameters
class TLLegacy(implicit p: Parameters) extends LazyModule with HasTileLinkParameters
{
// TL legacy clients don't support anything fancy
val node = TLClientNode(TLClientParameters(
sourceId = IdRange(0, 1 << tlClientXactIdBits)))
lazy val module = new LegacyLazyModuleImp(this) {
lazy val module = new LazyModuleImp(this) with HasTileLinkParameters {
val io = new Bundle {
val legacy = new ClientUncachedTileLinkIO()(p).flip
val legacy = new ClientUncachedTileLinkIO().flip
val out = node.bundleOut
}

42
src/main/scala/uncore/tilelink2/Monitor.scala
View File

@ -4,9 +4,31 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.{SourceInfo, SourceLine}
import config._
import diplomacy._
class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: SourceInfo) extends LazyModule
case class TLMonitorArgs(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: SourceInfo, p: Parameters)
abstract class TLMonitorBase(args: TLMonitorArgs) extends LazyModule()(args.p)
{
implicit val sourceInfo = args.sourceInfo
def legalize(bundle: TLBundleSnoop, edge: TLEdge): Unit
var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {}
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = args.gen().asInput
}
code_insertion(io.in, edge())
legalize(io.in, args.edge())
}
}
class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
{
def extra(implicit sourceInfo: SourceInfo) = {
sourceInfo match {
@ -409,21 +431,9 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
inflight := (inflight | a_set) & ~d_clr
}
def legalize(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
def legalize(bundle: TLBundleSnoop, edge: TLEdge) {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeSourceUnique(bundle, edge)
}
var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {}
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = gen().asInput
}
code_insertion(io.in, edge())
legalize(io.in, edge())(sourceInfo)
}
}

25
src/main/scala/uncore/tilelink2/Nodes.scala
View File

@ -4,9 +4,14 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import scala.collection.mutable.ListBuffer
case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]]
case object TLFuzzReadyValid extends Field[Boolean]
case object TLCombinationalCheck extends Field[Boolean]
object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
@ -20,24 +25,16 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_))))
}
var emitMonitors = true
var stressTestDecoupled = false
var combinationalCheck = false
def colour = "#000000" // black
override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString
override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString
def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
val monitor = if (emitMonitors) {
Some(LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo)))
} else {
None
}
def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
val monitor = p(TLMonitorBuilder)(TLMonitorArgs(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo, p))
(monitor, () => {
bi <> bo
monitor.foreach { _.module.io.in := TLBundleSnoop(bo) }
if (combinationalCheck) {
if (p(TLCombinationalCheck)) {
// It is forbidden for valid to depend on ready in TL2
// If someone did that, then this will create a detectable combinational loop
bo.a.ready := bi.a.ready && bo.a.valid
@ -46,7 +43,7 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
bi.d.ready := bo.d.ready && bi.d.valid
bo.e.ready := bi.e.ready && bo.e.valid
}
if (stressTestDecoupled) {
if (p(TLCombinationalCheck)) {
// Randomly stall the transfers
val allow = LFSRNoiseMaker(5)
bi.a.valid := bo.a.valid && allow(0)
@ -132,7 +129,7 @@ case class TLInternalInputNode(portParams: TLClientPortParameters) extends Inter
/** Synthesizeable unit tests */
import unittest._
class TLInputNodeTest extends UnitTest(500000) {
class TLInputNodeTest()(implicit p: Parameters) extends UnitTest(500000) {
class Acceptor extends LazyModule {
val node = TLInputNode()
val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
@ -168,7 +165,7 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor
override def labelI(ei: TLAsyncEdgeParameters) = ei.manager.depth.toString
override def labelO(eo: TLAsyncEdgeParameters) = eo.manager.depth.toString
def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
(None, () => { bi <> bo })
}

3
src/main/scala/uncore/tilelink2/RAMModel.scala
View File

@ -3,6 +3,7 @@
package uncore.tilelink2
import Chisel._
import config._
import diplomacy._
// We detect concurrent puts that put memory into an undefined state.
@ -20,7 +21,7 @@ import diplomacy._
// put, get, getAck, putAck => ok: detected by getAck (it sees busy>0) impossible for FIFO
// If FIFO, the getAck should check data even if its validity was wiped
class TLRAMModel(log: String = "") extends LazyModule
class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule
{
val node = TLIdentityNode()

10
src/main/scala/uncore/tilelink2/RegisterRouter.scala
View File

@ -3,6 +3,7 @@
package uncore.tilelink2
import Chisel._
import config._
import diplomacy._
import regmapper._
import scala.math.{min,max}
@ -79,21 +80,22 @@ object TLRegisterNode
// register mapped device from a totally abstract register mapped device.
// See GPIO.scala in this directory for an example
abstract class TLRegisterRouterBase(val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean) extends LazyModule
abstract class TLRegisterRouterBase(val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
{
val node = TLRegisterNode(address, concurrency, beatBytes, undefZero, executable)
val intnode = IntSourceNode(interrupts)
}
case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])
case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])(implicit val p: Parameters)
class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
{
implicit val p = arg.p
val interrupts = arg.interrupts
val in = arg.in
}
class TLRegBundle[P](val params: P, arg: TLRegBundleArg) extends TLRegBundleBase(arg)
class TLRegBundle[P](val params: P, arg: TLRegBundleArg)(implicit p: Parameters) extends TLRegBundleBase(arg)
class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
extends LazyModuleImp(router) with HasRegMap
@ -107,7 +109,7 @@ class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, r
class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp]
(val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
(bundleBuilder: TLRegBundleArg => B)
(moduleBuilder: (=> B, TLRegisterRouterBase) => M)
(moduleBuilder: (=> B, TLRegisterRouterBase) => M)(implicit p: Parameters)
extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable)
{
require (isPow2(size))

13
src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
View File

@ -3,6 +3,7 @@
package uncore.tilelink2
import Chisel._
import config._
import diplomacy._
import regmapper._
import unittest._
@ -213,7 +214,7 @@ trait RRTest0Module extends HasRegMap
regmap(RRTest0Map.map:_*)
}
class RRTest0(address: BigInt) extends TLRegisterRouter(address, 0, 32, 0, 4)(
class RRTest0(address: BigInt)(implicit p: Parameters) extends TLRegisterRouter(address, 0, 32, 0, 4)(
new TLRegBundle((), _) with RRTest0Bundle)(
new TLRegModule((), _, _) with RRTest0Module)
@ -250,11 +251,11 @@ trait RRTest1Module extends Module with HasRegMap
regmap(map:_*)
}
class RRTest1(address: BigInt) extends TLRegisterRouter(address, 0, 32, 6, 4)(
class RRTest1(address: BigInt)(implicit p: Parameters) extends TLRegisterRouter(address, 0, 32, 6, 4)(
new TLRegBundle((), _) with RRTest1Bundle)(
new TLRegModule((), _, _) with RRTest1Module)
class FuzzRRTest0 extends LazyModule {
class FuzzRRTest0()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val rrtr = LazyModule(new RRTest0(0x400))
@ -265,11 +266,11 @@ class FuzzRRTest0 extends LazyModule {
}
}
class TLRR0Test extends UnitTest(timeout = 500000) {
class TLRR0Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new FuzzRRTest0).module).io.finished
}
class FuzzRRTest1 extends LazyModule {
class FuzzRRTest1()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val rrtr = LazyModule(new RRTest1(0x400))
@ -280,7 +281,7 @@ class FuzzRRTest1 extends LazyModule {
}
}
class TLRR1Test extends UnitTest(timeout = 500000) {
class TLRR1Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new FuzzRRTest1).module).io.finished
}

7
src/main/scala/uncore/tilelink2/SRAM.scala
View File

@ -3,9 +3,10 @@
package uncore.tilelink2
import Chisel._
import config._
import diplomacy._
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
{
val node = TLManagerNode(TLManagerPortParameters(
Seq(TLManagerParameters(
@ -84,7 +85,7 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
/** Synthesizeable unit testing */
import unittest._
class TLRAMSimple(ramBeatBytes: Int) extends LazyModule {
class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
@ -97,6 +98,6 @@ class TLRAMSimple(ramBeatBytes: Int) extends LazyModule {
}
}
class TLRAMSimpleTest(ramBeatBytes: Int) extends UnitTest(timeout = 500000) {
class TLRAMSimpleTest(ramBeatBytes: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes)).module).io.finished
}

5
src/main/scala/uncore/tilelink2/SourceShrinker.scala
View File

@ -4,10 +4,11 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import scala.math.{min,max}
class TLSourceShrinker(maxInFlight: Int) extends LazyModule
class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyModule
{
require (maxInFlight > 0)
@ -78,7 +79,7 @@ class TLSourceShrinker(maxInFlight: Int) extends LazyModule
object TLSourceShrinker
{
// applied to the TL source node; y.node := TLSourceShrinker(n)(x.node)
def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val shrinker = LazyModule(new TLSourceShrinker(maxInFlight))
shrinker.node := x
shrinker.node

141
src/main/scala/uncore/tilelink2/ToAHB.scala Normal file
View File

@ -0,0 +1,141 @@
// See LICENSE.SiFive for license details.
package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import util.PositionalMultiQueue
import uncore.ahb._
import scala.math.{min, max}
import AHBParameters._
case class TLToAHBNode() extends MixedNode(TLImp, AHBImp)(
dFn = { case (1, Seq(TLClientPortParameters(clients, unsafeAtomics, minLatency))) =>
val masters = clients.map { case c => AHBMasterParameters(nodePath = c.nodePath) }
Seq(AHBMasterPortParameters(masters))
},
uFn = { case (1, Seq(AHBSlavePortParameters(slaves, beatBytes))) =>
val managers = slaves.map { case s =>
TLManagerParameters(
address = s.address,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,
supportsGet = s.supportsRead,
supportsPutFull = s.supportsWrite, // but not PutPartial
fifoId = Some(0)) // a common FIFO domain
}
Seq(TLManagerPortParameters(managers, beatBytes, 1, 1))
},
numPO = 1 to 1,
numPI = 1 to 1)
class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
{
val node = TLToAHBNode()
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val in = node.bundleIn
val out = node.bundleOut
}
val in = io.in(0)
val out = io.out(0)
val edgeIn = node.edgesIn(0)
val edgeOut = node.edgesOut(0)
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val lgMax = log2Ceil(maxTransfer)
val lgBytes = log2Ceil(beatBytes)
// AHB has no cache coherence
in.b.valid := Bool(false)
in.c.ready := Bool(true)
in.e.ready := Bool(true)
// We need a skidpad to capture D output:
// We cannot know if the D response will be accepted until we have
// presented it on D as valid. We also can't back-pressure AHB in the
// data phase. Therefore, we must have enough space to save the data
// phase result. Whenever we have a queued response, we can not allow
// AHB to present new responses, so we must quash the address phase.
val d = Wire(in.d)
in.d <> Queue(d, 1, flow = true)
val a_quash = in.d.valid && !in.d.ready
// Record what is coming out in d_phase
val d_valid = RegInit(Bool(false))
val d_hasData = Reg(Bool())
val d_error = Reg(Bool())
val d_addr_lo = Reg(UInt(width = lgBytes))
val d_source = Reg(UInt())
val d_size = Reg(UInt())
when (out.hreadyout) { d_error := d_error || out.hresp }
when (d.fire()) { d_valid := Bool(false) }
d.valid := d_valid && out.hreadyout
d.bits := edgeIn.AccessAck(d_addr_lo, UInt(0), d_source, d_size, out.hrdata, out.hresp || d_error)
d.bits.opcode := Mux(d_hasData, TLMessages.AccessAckData, TLMessages.AccessAck)
// We need an irrevocable input for AHB to stall on read bursts
// We also need the values to NOT change when valid goes low => 1 entry only
val a = Queue(in.a, 1, flow = combinational, pipe = !combinational)
val a_valid = a.valid && !a_quash
// This is lot like TLEdge.firstlast, but counts beats also for single-beat TL types
val a_size = edgeIn.size(a.bits)
val a_beats1 = UIntToOH1(a_size, lgMax) >> lgBytes
val a_counter = RegInit(UInt(0, width = log2Up(maxTransfer/beatBytes)))
val a_counter1 = a_counter - UInt(1)
val a_first = a_counter === UInt(0)
val a_last = a_counter === UInt(1) || a_beats1 === UInt(0)
val a_offset = (a_beats1 & ~a_counter1) << lgBytes
val a_hasData = edgeIn.hasData(a.bits)
// Expand no-data A-channel requests into multiple beats
a.ready := (a_hasData || a_last) && out.hreadyout && !a_quash
when (a_valid && out.hreadyout) {
a_counter := Mux(a_first, a_beats1, a_counter1)
d_valid := !a_hasData || a_last
// Record what will be in the data phase
when (a_first) {
d_hasData := !a_hasData
d_error := Bool(false)
d_addr_lo := a.bits.address
d_source := a.bits.source
d_size := a.bits.size
}
}
// Transform TL size into AHB hsize+hburst
val a_size_bits = a_size.getWidth
val a_sizeDelta = Cat(UInt(0, width = 1), a_size) - UInt(lgBytes+1)
val a_singleBeat = a_sizeDelta(a_size_bits)
val a_logBeats1 = a_sizeDelta(a_size_bits-1, 0)
out.hmastlock := Bool(false) // for now
out.htrans := Mux(a_valid, Mux(a_first, TRANS_NONSEQ, TRANS_SEQ), Mux(a_first, TRANS_IDLE, TRANS_BUSY))
out.hsel := Bool(true)
out.hready := out.hreadyout
out.hwrite := a_hasData
out.haddr := a.bits.address | a_offset
out.hsize := Mux(a_singleBeat, a.bits.size, UInt(lgBytes))
out.hburst := Mux(a_singleBeat, BURST_SINGLE, (a_logBeats1<<1) | UInt(1))
out.hprot := PROT_DEFAULT
out.hwdata := RegEnable(a.bits.data, a.fire())
}
}
object TLToAHB
{
// applied to the TL source node; y.node := TLToAHB()(x.node)
def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
val axi4 = LazyModule(new TLToAHB(combinational))
axi4.node := x
axi4.node
}
}

5
src/main/scala/uncore/tilelink2/ToAXI4.scala
View File

@ -4,6 +4,7 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import util.PositionalMultiQueue
import uncore.axi4._
@ -35,7 +36,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)(
numPO = 1 to 1,
numPI = 1 to 1)
class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule
class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
{
val node = TLToAXI4Node(idBits)
@ -229,7 +230,7 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule
object TLToAXI4
{
// applied to the TL source node; y.node := TLToAXI4(idBits)(x.node)
def apply(idBits: Int, combinational: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
def apply(idBits: Int, combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val axi4 = LazyModule(new TLToAXI4(idBits, combinational))
axi4.node := x
axi4.node

9
src/main/scala/uncore/tilelink2/WidthWidget.scala
View File

@ -4,11 +4,12 @@ package uncore.tilelink2
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import scala.math.{min,max}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
val node = TLAdapterNode(
clientFn = { case Seq(c) => c },
@ -166,7 +167,7 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
object TLWidthWidget
{
// applied to the TL source node; y.node := WidthWidget(x.node, 16)
def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node := x
widget.node
@ -176,7 +177,7 @@ object TLWidthWidget
/** Synthesizeable unit tests */
import unittest._
class TLRAMWidthWidget(first: Int, second: Int) extends LazyModule {
class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
@ -193,6 +194,6 @@ class TLRAMWidthWidget(first: Int, second: Int) extends LazyModule {
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int) extends UnitTest(timeout = 500000) {
class TLRAMWidthWidgetTest(little: Int, big: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big)).module).io.finished
}

11
src/main/scala/uncore/tilelink2/Xbar.scala
View File

@ -3,9 +3,10 @@
package uncore.tilelink2
import Chisel._
import config._
import diplomacy._
class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends LazyModule
class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p: Parameters) extends LazyModule
{
def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
@ -184,7 +185,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends Lazy
/** Synthesizeable unit tests */
import unittest._
class TLRAMXbar(nManagers: Int) extends LazyModule {
class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val xbar = LazyModule(new TLXbar)
@ -201,11 +202,11 @@ class TLRAMXbar(nManagers: Int) extends LazyModule {
}
}
class TLRAMXbarTest(nManagers: Int) extends UnitTest(timeout = 500000) {
class TLRAMXbarTest(nManagers: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new TLRAMXbar(nManagers)).module).io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int) extends LazyModule {
class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
@ -224,6 +225,6 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int) extends LazyModule {
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int) extends UnitTest(timeout = 5000000) {
class TLMulticlientXbarTest(nManagers: Int, nClients: Int)(implicit p: Parameters) extends UnitTest(timeout = 5000000) {
io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients)).module).io.finished
}