diff --git a/.travis.yml b/.travis.yml index 4e3c4905..0b30e900 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,37 +1,18 @@ git: submodules: false language: scala -# run on new infrastructure -sudo: false +sudo: required +services: + - docker cache: - apt: true directories: $HOME/.ivy2 - regression/install - emulator/verilator - -# packages needed to build riscv-tools -addons: - apt: - sources: - - ubuntu-toolchain-r-test - packages: - - gcc-4.8 - - g++-4.8 - - gperf - - autoconf - - automake - - autotools-dev - - libmpc-dev - - libmpfr-dev - - libgmp-dev - - gawk - - build-essential - - bison - - flex - - texinfo env: + global: + - CACHE_NAME=RocketChip + - RISCV=/opt/riscv + - TORTURE_CONFIG=default matrix: - SUITE=RocketSuiteA - SUITE=RocketSuiteB @@ -47,15 +28,9 @@ branches: - boom - /^hurricane.*$/ -install: - - make tools verilator -C regression SUITE=none - before_install: - - export CXX=g++-4.8 CC=gcc-4.8 + - docker pull hcook/docker-riscv script: - - make emulator-ndebug -C regression SUITE=$SUITE TORTURE_CONFIG=default - - make emulator-regression-tests -C regression SUITE=$SUITE TORTURE_CONFIG=default - -before_cache: - - ls -t regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf + - docker run -v /home/travis/build/ucb-bar/rocket-chip:/opt/riscv/test hcook/docker-riscv /bin/sh -c "which verilator; echo $INSTALLED_VERILATOR" + - docker run -v $HOME/.ivy2:/opt/riscv/test/.ivy2 -v /home/travis/build/ucb-bar/rocket-chip:/opt/riscv/test hcook/docker-riscv /bin/sh -c "make emulator-ndebug -C regression SUITE=$SUITE; make emulator-regression-tests -C regression SUITE=$SUITE" diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator index ea7c7e7d..59070d0f 100644 --- a/emulator/Makefrag-verilator +++ b/emulator/Makefrag-verilator @@ -22,8 +22,8 @@ $(generated_dir_debug)/%.fir $(generated_dir_debug)/%.prm $(generated_dir_debug) # Build and install our own Verilator, to work around versionining issues. VERILATOR_VERSION=3.884 -VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION) -INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator) +VERILATOR_SRCDIR ?= verilator/src/verilator-$(VERILATOR_VERSION) +INSTALLED_VERILATOR ?= $(abspath verilator/install/bin/verilator) $(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata touch $@ diff --git a/src/main/scala/util/Config.scala b/src/main/scala/config/Config.scala similarity index 100% rename from src/main/scala/util/Config.scala rename to src/main/scala/config/Config.scala diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 7896aaff..9a246271 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -31,7 +31,8 @@ case object BroadcastConfig extends Field[BroadcastConfig] case class BankedL2Config( nMemoryChannels: Int = 1, nBanksPerChannel: Int = 1, - coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case p => + coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case q => + implicit val p = q val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig) val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless)) (bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node)) @@ -54,9 +55,10 @@ trait HasCoreplexParameters { case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters -abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule -abstract class BareCoreplexBundle[+L <: BareCoreplex](_outer: L) extends Bundle { +abstract class BareCoreplex(implicit p: Parameters) extends LazyModule +abstract class BareCoreplexBundle[+L <: BareCoreplex](_outer: L) extends GenericParameterizedBundle(_outer) { val outer = _outer + implicit val p = outer.p } abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) { val outer = _outer @@ -96,7 +98,6 @@ trait CoreplexNetwork extends HasCoreplexParameters { trait CoreplexNetworkBundle extends HasCoreplexParameters { val outer: CoreplexNetwork - implicit val p = outer.p val mmio = outer.mmio.bundleOut val interrupts = outer.mmioInt.bundleIn } @@ -105,8 +106,6 @@ trait CoreplexNetworkModule extends HasCoreplexParameters { val outer: CoreplexNetwork val io: CoreplexNetworkBundle - implicit val p = outer.p - println("\nGenerated Address Map") for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) { val prot = (if (manager.supportsGet) "R" else "") + diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 475ad5b1..fb658c8a 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -4,8 +4,10 @@ package coreplex import Chisel._ -import junctions._ +import config._ import diplomacy._ +import junctions.PAddrBits +import rocket._ import uncore.tilelink._ import uncore.tilelink2._ import uncore.coherence._ @@ -13,10 +15,7 @@ import uncore.agents._ import uncore.devices._ import uncore.converters._ import uncore.util._ -import rocket._ import util._ -import util.ConfigUtils._ -import config._ class BaseCoreplexConfig extends Config ( { (pname,site,here) => @@ -95,11 +94,11 @@ class BaseCoreplexConfig extends Config ( nManagers = site(BankedL2Config).nBanks + 1 /* MMIO */, nCachingClients = 1, nCachelessClients = 1, - maxClientXacts = max_int( + maxClientXacts = List( // L1 cache site(DCacheKey).nMSHRs + 1 /* IOMSHR */, // RoCC - if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)), + if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)).max, maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2, maxManagerXacts = site(NAcquireTransactors) + 2, dataBeats = innerDataBeats, @@ -208,7 +207,7 @@ class WithStatelessBridge extends Config( (pname,site,here,up) => pname match { /* !!! FIXME case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (_, _) => - val pass = LazyModule(new TLBuffer(0)) + val pass = LazyModule(new TLBuffer(0)(site)) (pass.node, pass.node) }) */ diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 52824f47..7aabd9ea 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -3,9 +3,10 @@ package diplomacy import Chisel._ +import config._ import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo} -abstract class LazyModule +abstract class LazyModule()(implicit val p: Parameters) { protected[diplomacy] var bindings = List[() => Unit]() protected[diplomacy] var children = List[LazyModule]() @@ -115,4 +116,5 @@ abstract class LazyModuleImp(outer: LazyModule) extends Module suggestName(outer.instanceName) outer.instantiate() + implicit val p = outer.p } diff --git a/src/main/scala/diplomacy/Nodes.scala b/src/main/scala/diplomacy/Nodes.scala index bf001526..c01febf7 100644 --- a/src/main/scala/diplomacy/Nodes.scala +++ b/src/main/scala/diplomacy/Nodes.scala @@ -3,6 +3,7 @@ package diplomacy import Chisel._ +import config._ import scala.collection.mutable.ListBuffer import chisel3.internal.sourceinfo.SourceInfo @@ -15,7 +16,7 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data] def edgeI(pd: DI, pu: UI): EI def bundleI(ei: Seq[EI]): Vec[BI] def colour: String - def connect(bo: => BI, bi: => BI, e: => EI)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) + def connect(bo: => BI, bi: => BI, e: => EI)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) // optional methods to track node graph def mixI(pu: UI, node: InwardNode[DI, UI, BI]): UI = pu // insert node into parameters @@ -68,8 +69,8 @@ case class NodeHandle[DI, UI, BI <: Data, DO, UO, BO <: Data] trait InwardNodeHandle[DI, UI, BI <: Data] { val inward: InwardNode[DI, UI, BI] - def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = - inward.:=(h)(sourceInfo) + def := (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[LazyModule] = + inward.:=(h)(p, sourceInfo) } trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI, UI, BI] @@ -174,7 +175,7 @@ class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( lazy val bundleIn = wireI(flipI(inner.bundleI(edgesIn))) // connects the outward part of a node with the inward part of this node - override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = { + override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[LazyModule] = { val x = this // x := y val y = h.outward val info = sourceLine(sourceInfo, " at ", "") diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index 83e8e797..45cd5a79 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -16,7 +16,6 @@ import config._ import scala.math.max import coreplex._ import rocketchip._ -import util.ConfigUtils._ /** Actual testing target Configs */ @@ -193,10 +192,10 @@ class WithTraceGen extends Config( case BuildGroundTest => (p: Parameters) => Module(new GroundTestTraceGenerator()(p)) case GeneratorKey => TrafficGeneratorParameters( - maxRequests = 256, + maxRequests = 8192, startAddress = 0) case AddressBag => { - val nSets = 32 // L2 NSets + val nSets = 2 val nWays = 1 val blockOffset = site(CacheBlockOffsetBits) val nBeats = site(TLKey("L1toL2")).dataBeats diff --git a/src/main/scala/groundtest/TestHarness.scala b/src/main/scala/groundtest/TestHarness.scala index 906c973a..a7f523fe 100644 --- a/src/main/scala/groundtest/TestHarness.scala +++ b/src/main/scala/groundtest/TestHarness.scala @@ -8,11 +8,10 @@ import config._ import rocketchip._ import util._ -class TestHarness(q: Parameters) extends Module { +class TestHarness(implicit p: Parameters) extends Module { val io = new Bundle { val success = Bool(OUTPUT) } - implicit val p = q val dut = Module(LazyModule(new GroundTestTop).module) io.success := dut.io.success diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index 24676fe5..c1f22788 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -102,7 +102,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module val io = new GroundTestIO } -class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGroundTestParameters { +class GroundTestTile(implicit p: Parameters) extends LazyModule with HasGroundTestParameters { val dcacheParams = p.alterPartial { case CacheName => CacheName("L1D") case rocket.TLCacheEdge => cachedOut.edgesOut(0) diff --git a/src/main/scala/rocket/Dcache.scala b/src/main/scala/rocket/Dcache.scala index 60c7ea0e..c3e7cdf5 100644 --- a/src/main/scala/rocket/Dcache.scala +++ b/src/main/scala/rocket/Dcache.scala @@ -42,7 +42,7 @@ class DCache(cfg: DCacheConfig, val scratch: () => Option[AddressSet])(implicit override lazy val module = new DCacheModule(this) } -class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModule(outer)(p) { +class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val maxUncachedInFlight = cfg.nMMIOs diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index d43d5e12..542ed4e1 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -129,7 +129,7 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val ordered = Bool(INPUT) } -abstract class HellaCache(val cfg: DCacheConfig)(implicit val p: Parameters) extends LazyModule { +abstract class HellaCache(val cfg: DCacheConfig)(implicit p: Parameters) extends LazyModule { val node = TLClientNode(TLClientParameters( sourceId = IdRange(0, cfg.nMSHRs + cfg.nMMIOs), supportsProbe = TransferSizes(p(CacheBlockBytes)))) @@ -142,7 +142,7 @@ class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends Bundle val mem = outer.node.bundleOut } -class HellaCacheModule(outer: HellaCache)(implicit val p: Parameters) extends LazyModuleImp(outer) +class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val cfg = outer.cfg val io = new HellaCacheBundle(outer) diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala index 3b00c473..bc0409a1 100644 --- a/src/main/scala/rocket/NBDcache.scala +++ b/src/main/scala/rocket/NBDcache.scala @@ -675,7 +675,7 @@ class NonBlockingDCache(cfg: DCacheConfig)(implicit p: Parameters) extends Hella override lazy val module = new NonBlockingDCacheModule(this) } -class NonBlockingDCacheModule(outer: NonBlockingDCache)(implicit p: Parameters) extends HellaCacheModule(outer)(p) { +class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule(outer) { require(isPow2(nWays)) // TODO: relax this require(p(DataScratchpadSize) == 0) diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index 3c0bd600..18f1c02d 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -11,7 +11,7 @@ import uncore.constants._ import uncore.tilelink2._ import uncore.util._ -class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule { +class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule { val coreDataBytes = p(XLen)/8 val node = TLManagerNode(TLManagerPortParameters( Seq(TLManagerParameters( diff --git a/src/main/scala/rocket/fpu.scala b/src/main/scala/rocket/fpu.scala index a29f12d3..ce5c6a21 100644 --- a/src/main/scala/rocket/fpu.scala +++ b/src/main/scala/rocket/fpu.scala @@ -308,17 +308,15 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) { val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 - dcmp.io.signaling := Bool(true) - val dcmp_out = (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR - val dcmp_exc = dcmp.io.exceptionFlags + dcmp.io.signaling := !in.rm(1) io.out.bits.toint := Mux(in.rm(0), classify_out, unrec_int) io.out.bits.store := unrec_mem io.out.bits.exc := Bits(0) when (in.cmd === FCMD_CMP) { - io.out.bits.toint := dcmp_out - io.out.bits.exc := dcmp_exc + io.out.bits.toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR + io.out.bits.exc := dcmp.io.exceptionFlags } when (in.cmd === FCMD_CVT_IF) { val minXLen = 32 diff --git a/src/main/scala/rocket/rocc.scala b/src/main/scala/rocket/rocc.scala index 15e32c6e..ee6a46e6 100644 --- a/src/main/scala/rocket/rocc.scala +++ b/src/main/scala/rocket/rocc.scala @@ -42,10 +42,10 @@ class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) { class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) { val cmd = Decoupled(new RoCCCommand).flip val resp = Decoupled(new RoCCResponse) - val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => CacheName("L1D") })) + val mem = new HellaCacheIO val busy = Bool(OUTPUT) val interrupt = Bool(OUTPUT) - + // These should be handled differently, eventually val autl = new ClientUncachedTileLinkIO val utl = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO) diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala index ca134251..ec0e7ff1 100644 --- a/src/main/scala/rocket/tile.scala +++ b/src/main/scala/rocket/tile.scala @@ -54,9 +54,9 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { cachedOut := dcache.node uncachedOut := TLHintHandler()(ucLegacy.node) val masterNodes = List(cachedOut, uncachedOut) - + (slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) } - + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val cached = cachedOut.bundleOut @@ -95,7 +95,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { cmdRouter.io.in <> core.io.rocc.cmd val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) => - val rocc = accelParams.generator(p.alterPartial({ + val rocc = accelParams.generator(dcacheParams.alterPartial({ case RoccNMemChannels => accelParams.nMemChannels case RoccNPTWPorts => accelParams.nPTWPorts })) diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index 0fff7244..442ffcf7 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -12,15 +12,13 @@ import uncore.devices._ import util._ import rocket._ -/** Enable or disable monitoring of Diplomatic buses */ -case object TLEmitMonitors extends Field[Boolean] - -abstract class BareTop(implicit val p: Parameters) extends LazyModule { +abstract class BareTop(implicit p: Parameters) extends LazyModule { TopModule.contents = Some(this) } -abstract class BareTopBundle[+L <: BareTop](_outer: L) extends Bundle { +abstract class BareTopBundle[+L <: BareTop](_outer: L) extends GenericParameterizedBundle(_outer) { val outer = _outer + implicit val p = outer.p } abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) { @@ -32,8 +30,6 @@ abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _ trait TopNetwork extends HasPeripheryParameters { val module: TopNetworkModule - TLImp.emitMonitors = p(TLEmitMonitors) - // Add a SoC and peripheral bus val socBus = LazyModule(new TLXbar) val peripheryBus = LazyModule(new TLXbar) @@ -47,13 +43,11 @@ trait TopNetwork extends HasPeripheryParameters { trait TopNetworkBundle extends HasPeripheryParameters { val outer: TopNetwork - implicit val p = outer.p } trait TopNetworkModule extends HasPeripheryParameters { val io: TopNetworkBundle val outer: TopNetwork - implicit val p = outer.p } /** Base Top with no Periphery */ diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala index b3348311..988c4e36 100644 --- a/src/main/scala/rocketchip/Configs.scala +++ b/src/main/scala/rocketchip/Configs.scala @@ -8,7 +8,7 @@ import junctions._ import rocket._ import diplomacy._ import uncore.agents._ -import uncore.tilelink._ +import uncore.tilelink2._ import uncore.devices._ import uncore.converters._ import util._ @@ -21,8 +21,11 @@ import config._ class BasePlatformConfig extends Config( (pname,site,here) => pname match { + // TileLink connection parameters + case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args))) + case TLFuzzReadyValid => false + case TLCombinationalCheck => false //Memory Parameters - case TLEmitMonitors => true case NExtTopInterrupts => 2 case SOCBusConfig => site(L1toL2Config) case PeripheryBusConfig => TLBusConfig(beatBytes = 4) @@ -143,16 +146,9 @@ class With64BitPeriphery extends Config ( } ) -class WithTLMonitors extends Config ( - (pname, site, here) => pname match { - case TLEmitMonitors => true - case _ => throw new CDEMatchError - } -) - class WithoutTLMonitors extends Config ( (pname, site, here) => pname match { - case TLEmitMonitors => false + case TLMonitorBuilder => (args: TLMonitorArgs) => None case _ => throw new CDEMatchError } ) diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala index 2bcb90de..7de32c20 100644 --- a/src/main/scala/rocketchip/TestHarness.scala +++ b/src/main/scala/rocketchip/TestHarness.scala @@ -9,11 +9,10 @@ import diplomacy._ import coreplex._ import uncore.axi4._ -class TestHarness(q: Parameters) extends Module { +class TestHarness()(implicit p: Parameters) extends Module { val io = new Bundle { val success = Bool(OUTPUT) } - implicit val p = q val dut = Module(LazyModule(new ExampleRocketTop).module) for (int <- dut.io.interrupts(0)) diff --git a/src/main/scala/uncore/ahb/Bundles.scala b/src/main/scala/uncore/ahb/Bundles.scala new file mode 100644 index 00000000..5822ff74 --- /dev/null +++ b/src/main/scala/uncore/ahb/Bundles.scala @@ -0,0 +1,35 @@ +// See LICENSE.SiFive for license details. + +package uncore.ahb + +import Chisel._ +import util.GenericParameterizedBundle + +abstract class AHBBundleBase(params: AHBBundleParameters) extends GenericParameterizedBundle(params) + +// Signal directions are from the master's point-of-view +class AHBBundle(params: AHBBundleParameters) extends AHBBundleBase(params) +{ + // Flow control signals from the master + val hmastlock = Bool(OUTPUT) + val htrans = UInt(OUTPUT, width = params.transBits) + val hsel = Bool(OUTPUT) // on a master, drive this with true + val hready = Bool(OUTPUT) // on a master, drive this from readyout + + // Payload signals + val hwrite = Bool(OUTPUT) + val haddr = UInt(OUTPUT, width = params.addrBits) + val hsize = UInt(OUTPUT, width = params.sizeBits) + val hburst = UInt(OUTPUT, width = params.burstBits) + val hprot = UInt(OUTPUT, width = params.protBits) + val hwdata = UInt(OUTPUT, width = params.dataBits) + + val hreadyout = Bool(INPUT) + val hresp = Bool(INPUT) + val hrdata = UInt(INPUT, width = params.dataBits) +} + +object AHBBundle +{ + def apply(params: AHBBundleParameters) = new AHBBundle(params) +} diff --git a/src/main/scala/uncore/ahb/Nodes.scala b/src/main/scala/uncore/ahb/Nodes.scala new file mode 100644 index 00000000..79776111 --- /dev/null +++ b/src/main/scala/uncore/ahb/Nodes.scala @@ -0,0 +1,59 @@ +// See LICENSE.SiFive for license details. + +package uncore.ahb + +import Chisel._ +import chisel3.internal.sourceinfo.SourceInfo +import config._ +import diplomacy._ + +object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBEdgeParameters, AHBBundle] +{ + def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu) + def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu) + def bundleO(eo: Seq[AHBEdgeParameters]): Vec[AHBBundle] = { + require (!eo.isEmpty) + Vec(eo.size, AHBBundle(eo.map(_.bundle).reduce(_.union(_)))) + } + def bundleI(ei: Seq[AHBEdgeParameters]): Vec[AHBBundle] = { + require (!ei.isEmpty) + Vec(ei.size, AHBBundle(ei.map(_.bundle).reduce(_.union(_)))) + } + + def colour = "#00ccff" // bluish + override def labelI(ei: AHBEdgeParameters) = (ei.slave.beatBytes * 8).toString + override def labelO(eo: AHBEdgeParameters) = (eo.slave.beatBytes * 8).toString + + def connect(bo: => AHBBundle, bi: => AHBBundle, ei: => AHBEdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { + (None, () => { bi <> bo }) + } + + override def mixO(pd: AHBMasterPortParameters, node: OutwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]): AHBMasterPortParameters = + pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) }) + override def mixI(pu: AHBSlavePortParameters, node: InwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]): AHBSlavePortParameters = + pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) }) +} + +// Nodes implemented inside modules +case class AHBIdentityNode() extends IdentityNode(AHBImp) +case class AHBMasterNode(portParams: AHBMasterPortParameters, numPorts: Range.Inclusive = 1 to 1) + extends SourceNode(AHBImp)(portParams, numPorts) +case class AHBSlaveNode(portParams: AHBSlavePortParameters, numPorts: Range.Inclusive = 1 to 1) + extends SinkNode(AHBImp)(portParams, numPorts) +case class AHBAdapterNode( + masterFn: Seq[AHBMasterPortParameters] => AHBMasterPortParameters, + slaveFn: Seq[AHBSlavePortParameters] => AHBSlavePortParameters, + numMasterPorts: Range.Inclusive = 1 to 1, + numSlavePorts: Range.Inclusive = 1 to 1) + extends InteriorNode(AHBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts) + +// Nodes passed from an inner module +case class AHBOutputNode() extends OutputNode(AHBImp) +case class AHBInputNode() extends InputNode(AHBImp) + +// Nodes used for external ports +case class AHBBlindOutputNode(portParams: AHBSlavePortParameters) extends BlindOutputNode(AHBImp)(portParams) +case class AHBBlindInputNode(portParams: AHBMasterPortParameters) extends BlindInputNode(AHBImp)(portParams) + +case class AHBInternalOutputNode(portParams: AHBSlavePortParameters) extends InternalOutputNode(AHBImp)(portParams) +case class AHBInternalInputNode(portParams: AHBMasterPortParameters) extends InternalInputNode(AHBImp)(portParams) diff --git a/src/main/scala/uncore/ahb/Parameters.scala b/src/main/scala/uncore/ahb/Parameters.scala new file mode 100644 index 00000000..1af5773c --- /dev/null +++ b/src/main/scala/uncore/ahb/Parameters.scala @@ -0,0 +1,99 @@ +// See LICENSE.SiFive for license details. + +package uncore.ahb + +import Chisel._ +import config._ +import diplomacy._ +import scala.math.max + +case class AHBSlaveParameters( + address: Seq[AddressSet], + regionType: RegionType.T = RegionType.GET_EFFECTS, + executable: Boolean = false, // processor can execute from this memory + nodePath: Seq[BaseNode] = Seq(), + supportsWrite: TransferSizes = TransferSizes.none, + supportsRead: TransferSizes = TransferSizes.none) +{ + address.foreach { a => require (a.finite) } + address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) } + + val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") + val maxTransfer = max(supportsWrite.max, supportsRead.max) + val maxAddress = address.map(_.max).max + val minAlignment = address.map(_.alignment).min + + // The device had better not support a transfer larger than it's alignment + require (minAlignment >= maxTransfer) +} + +case class AHBSlavePortParameters( + slaves: Seq[AHBSlaveParameters], + beatBytes: Int) +{ + require (!slaves.isEmpty) + require (isPow2(beatBytes)) + + val maxTransfer = slaves.map(_.maxTransfer).max + val maxAddress = slaves.map(_.maxAddress).max + + // Check the link is not pointlessly wide + require (maxTransfer >= beatBytes) + // Check that the link can be implemented in AHB + require (maxTransfer <= beatBytes * AHBParameters.maxTransfer) + + lazy val routingMask = AddressDecoder(slaves.map(_.address)) + def findSafe(address: UInt) = Vec(slaves.map(_.address.map(_.contains(address)).reduce(_ || _))) + def findFast(address: UInt) = Vec(slaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) + + // Require disjoint ranges for addresses + slaves.combinations(2).foreach { case Seq(x,y) => + x.address.foreach { a => y.address.foreach { b => + require (!a.overlaps(b)) + } } + } +} + +case class AHBMasterParameters( + nodePath: Seq[BaseNode] = Seq()) +{ + val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected") +} + +case class AHBMasterPortParameters( + masters: Seq[AHBMasterParameters]) + +case class AHBBundleParameters( + addrBits: Int, + dataBits: Int) +{ + require (dataBits >= 8) + require (addrBits >= 1) + require (isPow2(dataBits)) + + // Bring the globals into scope + val transBits = AHBParameters.transBits + val burstBits = AHBParameters.burstBits + val protBits = AHBParameters.protBits + val sizeBits = AHBParameters.sizeBits + + def union(x: AHBBundleParameters) = + AHBBundleParameters( + max(addrBits, x.addrBits), + max(dataBits, x.dataBits)) +} + +object AHBBundleParameters +{ + def apply(master: AHBMasterPortParameters, slave: AHBSlavePortParameters) = + new AHBBundleParameters( + addrBits = log2Up(slave.maxAddress+1), + dataBits = slave.beatBytes * 8) +} + +case class AHBEdgeParameters( + master: AHBMasterPortParameters, + slave: AHBSlavePortParameters) +{ + val bundle = AHBBundleParameters(master, slave) +} diff --git a/src/main/scala/uncore/ahb/Protocol.scala b/src/main/scala/uncore/ahb/Protocol.scala new file mode 100644 index 00000000..4dbd9f78 --- /dev/null +++ b/src/main/scala/uncore/ahb/Protocol.scala @@ -0,0 +1,40 @@ +// See LICENSE.SiFive for license details. + +package uncore.ahb + +import Chisel._ +import chisel3.util.{Irrevocable, IrrevocableIO} + +object AHBParameters +{ + // These are all fixed by the AHB standard: + val transBits = 2 + val burstBits = 3 + val protBits = 4 + val sizeBits = 3 // 8*2^s + + val TRANS_IDLE = UInt(0, width = transBits) // No transfer requested, not in a burst + val TRANS_BUSY = UInt(1, width = transBits) // No transfer requested, in a burst + val TRANS_NONSEQ = UInt(2, width = transBits) // First (potentially only) request in a burst + val TRANS_SEQ = UInt(3, width = transBits) // Following requests in a burst + + val BURST_SINGLE = UInt(0, width = burstBits) // Single access (no burst) + val BURST_INCR = UInt(1, width = burstBits) // Incrementing burst of arbitrary length, not crossing 1KB + val BURST_WRAP4 = UInt(2, width = burstBits) // 4-beat wrapping burst + val BURST_INCR4 = UInt(3, width = burstBits) // 4-beat incrementing burst + val BURST_WRAP8 = UInt(4, width = burstBits) // 8-beat wrapping burst + val BURST_INCR8 = UInt(5, width = burstBits) // 8-beat incrementing burst + val BURST_WRAP16 = UInt(6, width = burstBits) // 16-beat wrapping burst + val BURST_INCR16 = UInt(7, width = burstBits) // 16-beat incrementing burst + + val maxTransfer = 16 + + val RESP_OKAY = Bool(false) + val RESP_ERROR = Bool(true) + + val PROT_DATA = UInt(1, width = protBits) + val PROT_PRIVILEDGED = UInt(2, width = protBits) + val PROT_BUFFERABLE = UInt(4, width = protBits) + val PROT_CACHEABLE = UInt(8, width = protBits) + def PROT_DEFAULT = PROT_DATA | PROT_PRIVILEDGED +} diff --git a/src/main/scala/uncore/ahb/RegisterRouter.scala b/src/main/scala/uncore/ahb/RegisterRouter.scala new file mode 100644 index 00000000..88528bf4 --- /dev/null +++ b/src/main/scala/uncore/ahb/RegisterRouter.scala @@ -0,0 +1,112 @@ +// See LICENSE.SiFive for license details. + +package uncore.ahb + +import Chisel._ +import config._ +import diplomacy._ +import regmapper._ +import scala.math.{min,max} + +class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) + extends AHBSlaveNode(AHBSlavePortParameters( + Seq(AHBSlaveParameters( + address = Seq(address), + executable = executable, + supportsWrite = TransferSizes(1, min(address.alignment.toInt, beatBytes * AHBParameters.maxTransfer)), + supportsRead = TransferSizes(1, min(address.alignment.toInt, beatBytes * AHBParameters.maxTransfer)))), + beatBytes = beatBytes)) +{ + require (address.contiguous) + + // Calling this method causes the matching AHB bundle to be + // configured to route all requests to the listed RegFields. + def regmap(mapping: RegField.Map*) = { + val ahb = bundleIn(0) + + val indexBits = log2Up((address.mask+1)/beatBytes) + val params = RegMapperParams(indexBits, beatBytes, 1) + val in = Wire(Decoupled(new RegMapperInput(params))) + val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) + + val d_phase = RegInit(Bool(false)) + val d_taken = Reg(Bool()) + val d_read = Reg(Bool()) + val d_index = Reg(UInt(width = indexBits)) + val d_mask = Reg(UInt(width = beatBytes)) + + // Only send the request to the RR once + d_taken := d_phase && in.ready + in.valid := d_phase && !d_taken + + in.bits.read := d_read + in.bits.index := d_index + in.bits.data := ahb.hwdata + in.bits.mask := d_mask + in.bits.extra := UInt(0) + + when (ahb.hready) { d_phase := Bool(false) } + ahb.hreadyout := !d_phase || out.valid + ahb.hresp := AHBParameters.RESP_OKAY + ahb.hrdata := out.bits.data + + val request = ahb.htrans === AHBParameters.TRANS_NONSEQ || ahb.htrans === AHBParameters.TRANS_SEQ + when (ahb.hready && ahb.hsel && request) { + assert (!in.valid || in.ready) + d_phase := Bool(true) + d_taken := Bool(false) + d_read := !ahb.hwrite + d_index := ahb.haddr >> log2Ceil(beatBytes) + d_mask := uncore.tilelink2.maskGen(ahb.haddr, ahb.hsize, beatBytes) + } + + out.ready := Bool(true) + assert (d_phase || !out.valid) + } +} + +object AHBRegisterNode +{ + def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) = + new AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable) +} + +// These convenience methods below combine to make it possible to create a AHB +// register mapped device from a totally abstract register mapped device. + +abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule +{ + val node = AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable) + val intnode = uncore.tilelink2.IntSourceNode(interrupts) +} + +case class AHBRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AHBBundle])(implicit val p: Parameters) + +class AHBRegBundleBase(arg: AHBRegBundleArg) extends Bundle +{ + implicit val p = arg.p + val interrupts = arg.interrupts + val in = arg.in +} + +class AHBRegBundle[P](val params: P, arg: AHBRegBundleArg) extends AHBRegBundleBase(arg) + +class AHBRegModule[P, B <: AHBRegBundleBase](val params: P, bundleBuilder: => B, router: AHBRegisterRouterBase) + extends LazyModuleImp(router) with HasRegMap +{ + val io = bundleBuilder + val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0) + def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) +} + +class AHBRegisterRouter[B <: AHBRegBundleBase, M <: LazyModuleImp] + (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) + (bundleBuilder: AHBRegBundleArg => B) + (moduleBuilder: (=> B, AHBRegisterRouterBase) => M)(implicit p: Parameters) + extends AHBRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable) +{ + require (isPow2(size)) + // require (size >= 4096) ... not absolutely required, but highly recommended + + lazy val module = moduleBuilder(bundleBuilder(AHBRegBundleArg(intnode.bundleOut, node.bundleIn)), this) +} diff --git a/src/main/scala/uncore/ahb/SRAM.scala b/src/main/scala/uncore/ahb/SRAM.scala new file mode 100644 index 00000000..c173c973 --- /dev/null +++ b/src/main/scala/uncore/ahb/SRAM.scala @@ -0,0 +1,99 @@ +// See LICENSE.SiFive for license details. + +package uncore.ahb + +import Chisel._ +import config._ +import diplomacy._ + +class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule +{ + val node = AHBSlaveNode(AHBSlavePortParameters( + Seq(AHBSlaveParameters( + address = List(address), + regionType = RegionType.UNCACHED, + executable = executable, + supportsRead = TransferSizes(1, beatBytes * AHBParameters.maxTransfer), + supportsWrite = TransferSizes(1, beatBytes * AHBParameters.maxTransfer))), + beatBytes = beatBytes)) + + // We require the address range to include an entire beat (for the write mask) + require ((address.mask & (beatBytes-1)) == beatBytes-1) + + lazy val module = new LazyModuleImp(this) { + val io = new Bundle { + val in = node.bundleIn + } + + def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] = + if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail) + val mask = bigBits(address.mask >> log2Ceil(beatBytes)) + + val in = io.in(0) + + // The mask and address during the address phase + val a_access = in.htrans === AHBParameters.TRANS_NONSEQ || in.htrans === AHBParameters.TRANS_SEQ + val a_request = in.hready && in.hsel && a_access + val a_mask = uncore.tilelink2.maskGen(in.haddr, in.hsize, beatBytes) + val a_address = Cat((mask zip (in.haddr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse) + val a_write = in.hwrite + + // The data phase signals + val d_wdata = Vec.tabulate(beatBytes) { i => in.hwdata(8*(i+1)-1, 8*i) } + + // AHB writes must occur during the data phase; this poses a structural + // hazard with reads which must occur during the address phase. To solve + // this problem, we delay the writes until there is a free cycle. + // + // The idea is to record the address information from address phase and + // then as soon as possible flush the pending write. This cannot be done + // on a cycle when there is an address phase read, but on any other cycle + // the write will execute. In the case of reads following a write, the + // result must bypass data from the pending write into the read if they + // happen to have matching address. + + // Remove this once HoldUnless is in chisel3 + def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in) + + // Pending write? + val p_valid = RegInit(Bool(false)) + val p_address = Reg(a_address) + val p_mask = Reg(a_mask) + val p_latch_d = Reg(Bool()) + val p_wdata = holdUnless(d_wdata, p_latch_d) + + // Use single-ported memory with byte-write enable + val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8))) + + // Decide is the SRAM port is used for reading or (potentially) writing + val read = a_request && !a_write + // In case we choose to stall, we need to hold the read data + val d_rdata = holdUnless(mem.read(a_address, read), RegNext(read)) + // Whenever the port is not needed for reading, execute pending writes + when (!read && p_valid) { + p_valid := Bool(false) + mem.write(p_address, p_wdata, p_mask.toBools) + } + + // Record the request for later? + p_latch_d := a_request && a_write + when (a_request && a_write) { + p_valid := Bool(true) + p_address := a_address + p_mask := a_mask + } + + // Does the read need to be muxed with the previous write? + val a_bypass = a_address === p_address && p_valid + val d_bypass = RegEnable(a_bypass, a_request) + + // Mux in data from the pending write + val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata)) + map { case (m, (p, r)) => Mux(d_bypass && m, p, r) }) + + // Finally, the outputs + in.hreadyout := LFSR16(Bool(true))(0) // Bool(true) + in.hresp := AHBParameters.RESP_OKAY + in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0)) + } +} diff --git a/src/main/scala/uncore/ahb/Test.scala b/src/main/scala/uncore/ahb/Test.scala new file mode 100644 index 00000000..1c759fe3 --- /dev/null +++ b/src/main/scala/uncore/ahb/Test.scala @@ -0,0 +1,40 @@ +// See LICENSE.SiFive for license details. + +package uncore.ahb + +import Chisel._ +import config._ +import diplomacy._ +import uncore.tilelink2._ +import unittest._ + +class RRTest0(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter(address, 0, 32, 0, 4)( + new AHBRegBundle((), _) with RRTest0Bundle)( + new AHBRegModule((), _, _) with RRTest0Module) + +class RRTest1(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter(address, 0, 32, 1, 4, false)( + new AHBRegBundle((), _) with RRTest1Bundle)( + new AHBRegModule((), _, _) with RRTest1Module) + +class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule +{ + val fuzz = LazyModule(new TLFuzzer(5000)) + val model = LazyModule(new TLRAMModel("AHBFuzzMaster")) + var xbar = LazyModule(new AHBFanout) + val ram = LazyModule(new AHBRAM(AddressSet(0x0, 0xff))) + val gpio = LazyModule(new RRTest0(0x100)) + + model.node := fuzz.node + xbar.node := TLToAHB()(model.node) + ram.node := xbar.node + gpio.node := xbar.node + + lazy val module = new LazyModuleImp(this) with HasUnitTestIO { + io.finished := fuzz.module.io.finished + } +} + +class AHBBridgeTest()(implicit p: Parameters) extends UnitTest(500000) { + val dut = Module(LazyModule(new AHBFuzzBridge).module) + io.finished := dut.io.finished +} diff --git a/src/main/scala/uncore/ahb/Xbar.scala b/src/main/scala/uncore/ahb/Xbar.scala new file mode 100644 index 00000000..41ccf55f --- /dev/null +++ b/src/main/scala/uncore/ahb/Xbar.scala @@ -0,0 +1,50 @@ +// See LICENSE.SiFive for license details. + +package uncore.ahb + +import Chisel._ +import config._ +import diplomacy._ +import regmapper._ +import scala.math.{min,max} + +class AHBFanout()(implicit p: Parameters) extends LazyModule { + val node = AHBAdapterNode( + numSlavePorts = 1 to 1, + numMasterPorts = 1 to 32, + masterFn = { case Seq(m) => m }, + slaveFn = { seq => seq(0).copy(slaves = seq.flatMap(_.slaves)) }) + + lazy val module = new LazyModuleImp(this) { + val io = new Bundle { + val in = node.bundleIn + val out = node.bundleOut + } + + // Require consistent bus widths + val port0 = node.edgesIn(0).slave + node.edgesOut.foreach { edge => + val port = edge.slave + require (port.beatBytes == port0.beatBytes, + s"${port.slaves.map(_.name)} ${port.beatBytes} vs ${port0.slaves.map(_.name)} ${port0.beatBytes}") + } + + val port_addrs = node.edgesOut.map(_.slave.slaves.map(_.address).flatten) + val routingMask = AddressDecoder(port_addrs) + val route_addrs = port_addrs.map(_.map(_.widen(~routingMask)).distinct) + + val in = io.in(0) + val a_sel = Vec(route_addrs.map(seq => seq.map(_.contains(in.haddr)).reduce(_ || _))) + val d_sel = Reg(a_sel) + + when (in.hready) { d_sel := a_sel } + (a_sel zip io.out) foreach { case (sel, out) => + out := in + out.hsel := in.hsel && sel + } + + in.hreadyout := !Mux1H(d_sel, io.out.map(!_.hreadyout)) + in.hresp := Mux1H(d_sel, io.out.map(_.hresp)) + in.hrdata := Mux1H(d_sel, io.out.map(_.hrdata)) + } +} diff --git a/src/main/scala/uncore/ahb/package.scala b/src/main/scala/uncore/ahb/package.scala new file mode 100644 index 00000000..ed173388 --- /dev/null +++ b/src/main/scala/uncore/ahb/package.scala @@ -0,0 +1,11 @@ +// See LICENSE.SiFive for license details. + +package uncore + +import Chisel._ +import diplomacy._ + +package object ahb +{ + type AHBOutwardNode = OutwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle] +} diff --git a/src/main/scala/uncore/axi4/Buffer.scala b/src/main/scala/uncore/axi4/Buffer.scala index 1b2a7300..2dcefeb4 100644 --- a/src/main/scala/uncore/axi4/Buffer.scala +++ b/src/main/scala/uncore/axi4/Buffer.scala @@ -4,11 +4,12 @@ package uncore.axi4 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import scala.math.max // pipe is only used if a queue has depth = 1 -class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, pipe: Boolean = true) extends LazyModule +class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, pipe: Boolean = true)(implicit p: Parameters) extends LazyModule { require (aw >= 0) require (w >= 0) @@ -37,12 +38,12 @@ class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, p object AXI4Buffer { // applied to the AXI4 source node; y.node := AXI4Buffer(x.node) - def apply() (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(2)(x) - def apply(entries: Int) (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, true)(x) - def apply(entries: Int, pipe: Boolean) (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, entries, pipe)(x) - def apply(aw: Int, br: Int) (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, br, true)(x) - def apply(aw: Int, br: Int, pipe: Boolean)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br, pipe)(x) - def apply(aw: Int, w: Int, b: Int, ar: Int, r: Int, pipe: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = { + def apply() (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(2)(x) + def apply(entries: Int) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, true)(x) + def apply(entries: Int, pipe: Boolean) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, entries, pipe)(x) + def apply(aw: Int, br: Int) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, br, true)(x) + def apply(aw: Int, br: Int, pipe: Boolean)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br, pipe)(x) + def apply(aw: Int, w: Int, b: Int, ar: Int, r: Int, pipe: Boolean = true)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = { val buffer = LazyModule(new AXI4Buffer(aw, w, b, ar, r, pipe)) buffer.node := x buffer.node diff --git a/src/main/scala/uncore/axi4/Fragmenter.scala b/src/main/scala/uncore/axi4/Fragmenter.scala index ce29325a..f6cdf372 100644 --- a/src/main/scala/uncore/axi4/Fragmenter.scala +++ b/src/main/scala/uncore/axi4/Fragmenter.scala @@ -5,12 +5,13 @@ package uncore.axi4 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo import chisel3.util.IrrevocableIO +import config._ import diplomacy._ import scala.math.{min,max} import uncore.tilelink2.{leftOR, rightOR, UIntToOH1, OH1ToOH} // lite: masters all use only one ID => reads will not be interleaved -class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true) extends LazyModule +class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule { val maxBeats = 1 << AXI4Parameters.lenBits def expandTransfer(x: TransferSizes, beatBytes: Int, alignment: BigInt) = @@ -287,7 +288,7 @@ class AXI4FragmenterSideband(maxInFlight: Int, flow: Boolean = false) extends Mo object AXI4Fragmenter { // applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node) - def apply(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = { + def apply(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = { val fragmenter = LazyModule(new AXI4Fragmenter(lite, maxInFlight, combinational)) fragmenter.node := x fragmenter.node diff --git a/src/main/scala/uncore/axi4/Nodes.scala b/src/main/scala/uncore/axi4/Nodes.scala index 80397aa0..7d22b666 100644 --- a/src/main/scala/uncore/axi4/Nodes.scala +++ b/src/main/scala/uncore/axi4/Nodes.scala @@ -4,6 +4,7 @@ package uncore.axi4 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle] @@ -23,7 +24,7 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString override def labelO(eo: AXI4EdgeParameters) = (eo.slave.beatBytes * 8).toString - def connect(bo: => AXI4Bundle, bi: => AXI4Bundle, ei: => AXI4EdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { + def connect(bo: => AXI4Bundle, bi: => AXI4Bundle, ei: => AXI4EdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { (None, () => { bi <> bo }) } diff --git a/src/main/scala/uncore/axi4/Parameters.scala b/src/main/scala/uncore/axi4/Parameters.scala index 95c051b0..12e7b277 100644 --- a/src/main/scala/uncore/axi4/Parameters.scala +++ b/src/main/scala/uncore/axi4/Parameters.scala @@ -3,6 +3,7 @@ package uncore.axi4 import Chisel._ +import config._ import diplomacy._ import scala.math.max diff --git a/src/main/scala/uncore/axi4/RegisterRouter.scala b/src/main/scala/uncore/axi4/RegisterRouter.scala index fabf4722..df78c647 100644 --- a/src/main/scala/uncore/axi4/RegisterRouter.scala +++ b/src/main/scala/uncore/axi4/RegisterRouter.scala @@ -3,6 +3,7 @@ package uncore.axi4 import Chisel._ +import config._ import diplomacy._ import regmapper._ import scala.math.{min,max} @@ -77,16 +78,17 @@ object AXI4RegisterNode // These convenience methods below combine to make it possible to create a AXI4 // register mapped device from a totally abstract register mapped device. -abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean) extends LazyModule +abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule { val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable) val intnode = uncore.tilelink2.IntSourceNode(interrupts) } -case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle]) +case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])(implicit val p: Parameters) class AXI4RegBundleBase(arg: AXI4RegBundleArg) extends Bundle { + implicit val p = arg.p val interrupts = arg.interrupts val in = arg.in } @@ -104,7 +106,7 @@ class AXI4RegModule[P, B <: AXI4RegBundleBase](val params: P, bundleBuilder: => class AXI4RegisterRouter[B <: AXI4RegBundleBase, M <: LazyModuleImp] (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) (bundleBuilder: AXI4RegBundleArg => B) - (moduleBuilder: (=> B, AXI4RegisterRouterBase) => M) + (moduleBuilder: (=> B, AXI4RegisterRouterBase) => M)(implicit p: Parameters) extends AXI4RegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable) { require (isPow2(size)) diff --git a/src/main/scala/uncore/axi4/SRAM.scala b/src/main/scala/uncore/axi4/SRAM.scala index eac4b012..cc04c9fc 100644 --- a/src/main/scala/uncore/axi4/SRAM.scala +++ b/src/main/scala/uncore/axi4/SRAM.scala @@ -3,9 +3,10 @@ package uncore.axi4 import Chisel._ +import config._ import diplomacy._ -class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule +class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule { val node = AXI4SlaveNode(AXI4SlavePortParameters( Seq(AXI4SlaveParameters( diff --git a/src/main/scala/uncore/axi4/Test.scala b/src/main/scala/uncore/axi4/Test.scala index c0b3dfc3..2652b156 100644 --- a/src/main/scala/uncore/axi4/Test.scala +++ b/src/main/scala/uncore/axi4/Test.scala @@ -3,19 +3,20 @@ package uncore.axi4 import Chisel._ +import config._ import diplomacy._ import uncore.tilelink2._ import unittest._ -class RRTest0(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 0, 4)( +class RRTest0(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRouter(address, 0, 32, 0, 4)( new AXI4RegBundle((), _) with RRTest0Bundle)( new AXI4RegModule((), _, _) with RRTest0Module) -class RRTest1(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 6, 4, false)( +class RRTest1(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRouter(address, 0, 32, 6, 4, false)( new AXI4RegBundle((), _) with RRTest1Bundle)( new AXI4RegModule((), _, _) with RRTest1Module) -class AXI4LiteFuzzRAM extends LazyModule +class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val model = LazyModule(new TLRAMModel("AXI4LiteFuzzRAM")) @@ -33,12 +34,12 @@ class AXI4LiteFuzzRAM extends LazyModule } } -class AXI4LiteFuzzRAMTest extends UnitTest(500000) { +class AXI4LiteFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) { val dut = Module(LazyModule(new AXI4LiteFuzzRAM).module) io.finished := dut.io.finished } -class AXI4FullFuzzRAM extends LazyModule +class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val model = LazyModule(new TLRAMModel("AXI4FullFuzzRAM")) @@ -56,12 +57,12 @@ class AXI4FullFuzzRAM extends LazyModule } } -class AXI4FullFuzzRAMTest extends UnitTest(500000) { +class AXI4FullFuzzRAMTest(implicit p: Parameters) extends UnitTest(500000) { val dut = Module(LazyModule(new AXI4FullFuzzRAM).module) io.finished := dut.io.finished } -class AXI4FuzzMaster extends LazyModule +class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule { val node = AXI4OutputNode() val fuzz = LazyModule(new TLFuzzer(5000)) @@ -80,7 +81,7 @@ class AXI4FuzzMaster extends LazyModule } } -class AXI4FuzzSlave extends LazyModule +class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule { val node = AXI4InputNode() val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff))) @@ -94,7 +95,7 @@ class AXI4FuzzSlave extends LazyModule } } -class AXI4FuzzBridge extends LazyModule +class AXI4FuzzBridge()(implicit p: Parameters) extends LazyModule { val master = LazyModule(new AXI4FuzzMaster) val slave = LazyModule(new AXI4FuzzSlave) @@ -106,7 +107,7 @@ class AXI4FuzzBridge extends LazyModule } } -class AXI4BridgeTest extends UnitTest(500000) { +class AXI4BridgeTest()(implicit p: Parameters) extends UnitTest(500000) { val dut = Module(LazyModule(new AXI4FuzzBridge).module) io.finished := dut.io.finished } diff --git a/src/main/scala/uncore/axi4/ToTL.scala b/src/main/scala/uncore/axi4/ToTL.scala index 72a4e3f2..6519d5c3 100644 --- a/src/main/scala/uncore/axi4/ToTL.scala +++ b/src/main/scala/uncore/axi4/ToTL.scala @@ -4,6 +4,7 @@ package uncore.axi4 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import uncore.tilelink2._ @@ -30,7 +31,7 @@ case class AXI4ToTLNode() extends MixedNode(AXI4Imp, TLImp)( numPO = 1 to 1, numPI = 1 to 1) -class AXI4ToTL extends LazyModule +class AXI4ToTL()(implicit p: Parameters) extends LazyModule { val node = AXI4ToTLNode() @@ -176,7 +177,7 @@ class AXI4BundleRError(params: AXI4BundleParameters) extends AXI4BundleBase(para object AXI4ToTL { - def apply()(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = { + def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val tl = LazyModule(new AXI4ToTL) tl.node := x tl.node diff --git a/src/main/scala/uncore/devices/Debug.scala b/src/main/scala/uncore/devices/Debug.scala index 948f6c8b..9d5a3d65 100644 --- a/src/main/scala/uncore/devices/Debug.scala +++ b/src/main/scala/uncore/devices/Debug.scala @@ -332,8 +332,7 @@ object ToAsyncDebugBus } trait HasDebugModuleParameters { - val params : Parameters - implicit val p = params + implicit val p: Parameters val cfg = p(DMKey) } @@ -850,8 +849,8 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap { class TLDebugModule(address: BigInt = 0)(implicit p: Parameters) extends TLRegisterRouter(address, beatBytes=p(rocket.XLen)/8, executable=true)( - new TLRegBundle(p, _ ) with DebugModuleBundle)( - new TLRegModule(p, _, _) with DebugModule) + new TLRegBundle((), _ ) with DebugModuleBundle)( + new TLRegModule((), _, _) with DebugModule) /** Synchronizers for DebugBus diff --git a/src/main/scala/uncore/devices/Plic.scala b/src/main/scala/uncore/devices/Plic.scala index e5a67488..25d39fa0 100644 --- a/src/main/scala/uncore/devices/Plic.scala +++ b/src/main/scala/uncore/devices/Plic.scala @@ -52,7 +52,7 @@ object PLICConsts } /** Platform-Level Interrupt Controller */ -class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC000000)(implicit val p: Parameters) extends LazyModule +class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parameters) extends LazyModule { val contextsPerHart = if (supervisor) 2 else 1 require (maxPriorities >= 0) diff --git a/src/main/scala/uncore/devices/Prci.scala b/src/main/scala/uncore/devices/Prci.scala index 5c38987c..6354ddda 100644 --- a/src/main/scala/uncore/devices/Prci.scala +++ b/src/main/scala/uncore/devices/Prci.scala @@ -32,8 +32,7 @@ object ClintConsts } trait MixCoreplexLocalInterrupterParameters { - val params: Parameters - implicit val p = params + implicit val p: Parameters } trait CoreplexLocalInterrupterBundle extends Bundle with MixCoreplexLocalInterrupterParameters { @@ -83,10 +82,10 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep /** Power, Reset, Clock, Interrupt */ // Magic TL2 Incantation to create a TL2 Slave -class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Parameters) - extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)( - new TLRegBundle(p, _) with CoreplexLocalInterrupterBundle)( - new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule) +class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Parameters) + extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = true)( + new TLRegBundle((), _) with CoreplexLocalInterrupterBundle)( + new TLRegModule((), _, _) with CoreplexLocalInterrupterModule) { val globalConfigString = Seq( s"rtc {\n", diff --git a/src/main/scala/uncore/devices/Rom.scala b/src/main/scala/uncore/devices/Rom.scala index 88159dd6..4d39b75f 100644 --- a/src/main/scala/uncore/devices/Rom.scala +++ b/src/main/scala/uncore/devices/Rom.scala @@ -12,7 +12,7 @@ import uncore.tilelink2._ import uncore.util._ import config._ -class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4) extends LazyModule +class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule { val node = TLManagerNode(beatBytes, TLManagerParameters( address = List(AddressSet(base, size-1)), diff --git a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala index 6a8d0da8..667188b5 100644 --- a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala +++ b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala @@ -4,12 +4,13 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operationss. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. -class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true) extends LazyModule +class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) @@ -278,7 +279,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc object TLAtomicAutomata { // applied to the TL source node; y.node := TLAtomicAutomata(x.node) - def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = { + def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough)) atomics.node := x atomics.node @@ -290,7 +291,7 @@ import unittest._ //TODO ensure handler will pass through operations to clients that can handle them themselves -class TLRAMAtomicAutomata() extends LazyModule { +class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val model = LazyModule(new TLRAMModel) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) @@ -303,6 +304,6 @@ class TLRAMAtomicAutomata() extends LazyModule { } } -class TLRAMAtomicAutomataTest extends UnitTest(timeout = 500000) { +class TLRAMAtomicAutomataTest(implicit p: Parameters) extends UnitTest(timeout = 500000) { io.finished := Module(LazyModule(new TLRAMAtomicAutomata).module).io.finished } diff --git a/src/main/scala/uncore/tilelink2/Broadcast.scala b/src/main/scala/uncore/tilelink2/Broadcast.scala index ab39ada4..50cc55dc 100644 --- a/src/main/scala/uncore/tilelink2/Broadcast.scala +++ b/src/main/scala/uncore/tilelink2/Broadcast.scala @@ -3,10 +3,11 @@ package uncore.tilelink2 import Chisel._ +import config._ import diplomacy._ import scala.math.{min,max} -class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false) extends LazyModule +class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false)(implicit p: Parameters) extends LazyModule { require (lineBytes > 0 && isPow2(lineBytes)) require (numTrackers > 0) @@ -87,6 +88,8 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa val d_normal = Wire(in.d) val d_trackerOH = Vec(trackers.map { t => !t.idle && t.source === d_normal.bits.source }).asUInt + assert (!out.d.valid || !d_drop || out.d.bits.opcode === TLMessages.AccessAck) + out.d.ready := d_normal.ready || d_drop d_normal.valid := out.d.valid && !d_drop d_normal.bits := out.d.bits // truncates source @@ -102,6 +105,7 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa val d_last = edgeIn.last(d_normal) (trackers zip d_trackerOH.toBools) foreach { case (tracker, select) => tracker.d_last := select && d_normal.fire() && d_response && d_last + tracker.probedack := select && out.d.fire() && d_drop } // Incoming C can be: @@ -114,12 +118,12 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa val c_probeackdata = in.c.bits.opcode === TLMessages.ProbeAckData val c_releasedata = in.c.bits.opcode === TLMessages.ReleaseData val c_release = in.c.bits.opcode === TLMessages.Release + val c_trackerOH = trackers.map { t => t.line === (in.c.bits.address >> lineShift) } + val c_trackerSrc = Mux1H(c_trackerOH, trackers.map { _.source }) // Decrement the tracker's outstanding probe counter - val c_decrement = in.c.fire() && (c_probeack || c_probeackdata) - val c_last = edgeIn.last(in.c) - trackers foreach { tracker => - tracker.probeack := c_decrement && c_last && tracker.line === (in.c.bits.address >> lineShift) + (trackers zip c_trackerOH) foreach { case (tracker, select) => + tracker.probenack := in.c.fire() && c_probeack && select } val releaseack = Wire(in.d) @@ -131,8 +135,9 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa releaseack.bits := edgeIn.ReleaseAck(in.c.bits.address, UInt(0), in.c.bits.source, in.c.bits.size) val put_what = Mux(c_releasedata, TRANSFORM_B, DROP) + val put_who = Mux(c_releasedata, in.c.bits.source, c_trackerSrc) putfull.valid := in.c.valid && (c_probeackdata || c_releasedata) - putfull.bits := edgeOut.Put(Cat(put_what, in.c.bits.source), in.c.bits.address, in.c.bits.size, in.c.bits.data)._2 + putfull.bits := edgeOut.Put(Cat(put_what, put_who), in.c.bits.address, in.c.bits.size, in.c.bits.data)._2 // Combine ReleaseAck or the modified D TLArbiter.lowest(edgeOut, in.d, releaseack, d_normal) @@ -207,7 +212,8 @@ class TLBroadcastTracker(id: Int, lineBytes: Int, probeCountBits: Int, bufferles val in_a = Decoupled(new TLBundleA(edgeIn.bundle)).flip val out_a = Decoupled(new TLBundleA(edgeOut.bundle)) val probe = UInt(INPUT, width = probeCountBits) - val probeack = Bool(INPUT) + val probenack = Bool(INPUT) + val probedack = Bool(INPUT) val d_last = Bool(INPUT) val e_last = Bool(INPUT) val source = UInt(OUTPUT) // the source awaiting D response @@ -246,9 +252,10 @@ class TLBroadcastTracker(id: Int, lineBytes: Int, probeCountBits: Int, bufferles assert (!idle) idle := Bool(true) } - when (io.probeack) { + + when (io.probenack || io.probedack) { assert (count > UInt(0)) - count := count - UInt(1) + count := count - Mux(io.probenack && io.probedack, UInt(2), UInt(1)) } io.idle := idle diff --git a/src/main/scala/uncore/tilelink2/Buffer.scala b/src/main/scala/uncore/tilelink2/Buffer.scala index 425fb077..56a4070a 100644 --- a/src/main/scala/uncore/tilelink2/Buffer.scala +++ b/src/main/scala/uncore/tilelink2/Buffer.scala @@ -4,11 +4,12 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import scala.math.{min,max} // pipe is only used if a queue has depth = 1 -class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe: Boolean = true) extends LazyModule +class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe: Boolean = true)(implicit p: Parameters) extends LazyModule { require (a >= 0) require (b >= 0) @@ -49,12 +50,12 @@ class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe: object TLBuffer { // applied to the TL source node; y.node := TLBuffer(x.node) - def apply() (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(2)(x) - def apply(entries: Int) (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(entries, true)(x) - def apply(entries: Int, pipe: Boolean) (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(entries, entries, pipe)(x) - def apply(ace: Int, bd: Int) (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, true)(x) - def apply(ace: Int, bd: Int, pipe: Boolean)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace, pipe)(x) - def apply(a: Int, b: Int, c: Int, d: Int, e: Int, pipe: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = { + def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(2)(x) + def apply(entries: Int) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(entries, true)(x) + def apply(entries: Int, pipe: Boolean) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(entries, entries, pipe)(x) + def apply(ace: Int, bd: Int) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, true)(x) + def apply(ace: Int, bd: Int, pipe: Boolean)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace, pipe)(x) + def apply(a: Int, b: Int, c: Int, d: Int, e: Int, pipe: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e, pipe)) buffer.node := x buffer.node diff --git a/src/main/scala/uncore/tilelink2/Crossing.scala b/src/main/scala/uncore/tilelink2/Crossing.scala index 169b358b..f0eb8caf 100644 --- a/src/main/scala/uncore/tilelink2/Crossing.scala +++ b/src/main/scala/uncore/tilelink2/Crossing.scala @@ -4,10 +4,11 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import util._ -class TLAsyncCrossingSource(sync: Int = 3) extends LazyModule +class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = TLAsyncSourceNode() @@ -41,7 +42,7 @@ class TLAsyncCrossingSource(sync: Int = 3) extends LazyModule } } -class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3) extends LazyModule +class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(depth) @@ -77,7 +78,7 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3) extends LazyModule object TLAsyncCrossingSource { // applied to the TL source node; y.node := TLAsyncCrossingSource()(x.node) - def apply(sync: Int = 3)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLAsyncOutwardNode = { + def apply(sync: Int = 3)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLAsyncOutwardNode = { val source = LazyModule(new TLAsyncCrossingSource(sync)) source.node := x source.node @@ -87,14 +88,14 @@ object TLAsyncCrossingSource object TLAsyncCrossingSink { // applied to the TL source node; y.node := TLAsyncCrossingSink()(x.node) - def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = { + def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val sink = LazyModule(new TLAsyncCrossingSink(depth, sync)) sink.node := x sink.node } } -class TLAsyncCrossing(depth: Int = 8, sync: Int = 3) extends LazyModule +class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule { val nodeIn = TLInputNode() val nodeOut = TLOutputNode() @@ -136,7 +137,7 @@ class TLAsyncCrossing(depth: Int = 8, sync: Int = 3) extends LazyModule /** Synthesizeable unit tests */ import unittest._ -class TLRAMCrossing extends LazyModule { +class TLRAMCrossing(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val fuzz = LazyModule(new TLFuzzer(5000)) @@ -167,6 +168,6 @@ class TLRAMCrossing extends LazyModule { } } -class TLRAMCrossingTest extends UnitTest(timeout = 500000) { +class TLRAMCrossingTest(implicit p: Parameters) extends UnitTest(timeout = 500000) { io.finished := Module(LazyModule(new TLRAMCrossing).module).io.finished } diff --git a/src/main/scala/uncore/tilelink2/Example.scala b/src/main/scala/uncore/tilelink2/Example.scala index 8af96528..db102fc0 100644 --- a/src/main/scala/uncore/tilelink2/Example.scala +++ b/src/main/scala/uncore/tilelink2/Example.scala @@ -3,6 +3,7 @@ package uncore.tilelink2 import Chisel._ +import config._ import regmapper._ case class ExampleParams(num: Int, address: BigInt) @@ -33,6 +34,6 @@ trait ExampleModule extends HasRegMap } // Create a concrete TL2 version of the abstract Example slave -class TLExample(p: ExampleParams) extends TLRegisterRouter(p.address, 4)( - new TLRegBundle(p, _) with ExampleBundle)( - new TLRegModule(p, _, _) with ExampleModule) +class TLExample(params: ExampleParams)(implicit p: Parameters) extends TLRegisterRouter(params.address, 4)( + new TLRegBundle(params, _) with ExampleBundle)( + new TLRegModule(params, _, _) with ExampleModule) diff --git a/src/main/scala/uncore/tilelink2/Filter.scala b/src/main/scala/uncore/tilelink2/Filter.scala index a834b5f4..b6ddb9ea 100644 --- a/src/main/scala/uncore/tilelink2/Filter.scala +++ b/src/main/scala/uncore/tilelink2/Filter.scala @@ -4,10 +4,11 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import scala.math.{min,max} -class TLFilter(select: AddressSet) extends LazyModule +class TLFilter(select: AddressSet)(implicit p: Parameters) extends LazyModule { val node = TLAdapterNode( clientFn = { case Seq(cp) => cp }, @@ -44,7 +45,7 @@ class TLFilter(select: AddressSet) extends LazyModule object TLFilter { // applied to the TL source node; y.node := TLBuffer(x.node) - def apply(select: AddressSet)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = { + def apply(select: AddressSet)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val filter = LazyModule(new TLFilter(select)) filter.node := x filter.node diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index 1c95c78e..63197e63 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -4,6 +4,7 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import scala.math.{min,max} @@ -13,7 +14,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false)(implicit p: Parameters) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) @@ -253,7 +254,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = object TLFragmenter { // applied to the TL source node; y.node := TLFragmenter(x.node, 256, 4) - def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = { + def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin)) fragmenter.node := x fragmenter.node @@ -263,7 +264,7 @@ object TLFragmenter /** Synthesizeable unit tests */ import unittest._ -class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int) extends LazyModule { +class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val model = LazyModule(new TLRAMModel) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) @@ -276,6 +277,6 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int) extends LazyModule { } } -class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int) extends UnitTest(timeout = 500000) { +class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) { io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize)).module).io.finished } diff --git a/src/main/scala/uncore/tilelink2/Fuzzer.scala b/src/main/scala/uncore/tilelink2/Fuzzer.scala index 9122545f..4fab2385 100644 --- a/src/main/scala/uncore/tilelink2/Fuzzer.scala +++ b/src/main/scala/uncore/tilelink2/Fuzzer.scala @@ -3,6 +3,7 @@ package uncore.tilelink2 import Chisel._ +import config._ import diplomacy._ class IDMapGenerator(numIds: Int) extends Module { @@ -85,7 +86,7 @@ class TLFuzzer( (wide: Int, increment: Bool, abs_values: Int) => LFSRNoiseMaker(wide=wide, increment=increment) } - ) extends LazyModule + )(implicit p: Parameters) extends LazyModule { val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight))) @@ -213,7 +214,7 @@ class TLFuzzer( /** Synthesizeable integration test */ import unittest._ -class TLFuzzRAM extends LazyModule +class TLFuzzRAM()(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("TLFuzzRAM")) val ram = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff))) @@ -253,7 +254,7 @@ class TLFuzzRAM extends LazyModule } } -class TLFuzzRAMTest extends UnitTest(500000) { +class TLFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) { val dut = Module(LazyModule(new TLFuzzRAM).module) io.finished := dut.io.finished } diff --git a/src/main/scala/uncore/tilelink2/HintHandler.scala b/src/main/scala/uncore/tilelink2/HintHandler.scala index 1542f792..d9540b52 100644 --- a/src/main/scala/uncore/tilelink2/HintHandler.scala +++ b/src/main/scala/uncore/tilelink2/HintHandler.scala @@ -5,10 +5,11 @@ package uncore.tilelink2 import scala.math.min import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ // Acks Hints for managers that don't support them or Acks all Hints if !passthrough -class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends LazyModule +class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { val node = TLAdapterNode( clientFn = { case Seq(c) => if (!supportClients) c else c.copy(minLatency = min(1, c.minLatency), clients = c.clients .map(_.copy(supportsHint = TransferSizes(1, c.maxTransfer)))) }, @@ -100,7 +101,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f object TLHintHandler { // applied to the TL source node; y.node := TLHintHandler(x.node) - def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = { + def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough)) hints.node := x hints.node @@ -112,7 +113,7 @@ import unittest._ //TODO ensure handler will pass through hints to clients that can handle them themselves -class TLRAMHintHandler() extends LazyModule { +class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val model = LazyModule(new TLRAMModel) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) @@ -125,6 +126,6 @@ class TLRAMHintHandler() extends LazyModule { } } -class TLRAMHintHandlerTest extends UnitTest(timeout = 500000) { +class TLRAMHintHandlerTest()(implicit p: Parameters) extends UnitTest(timeout = 500000) { io.finished := Module(LazyModule(new TLRAMHintHandler).module).io.finished } diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala index 241c944f..eac638ba 100644 --- a/src/main/scala/uncore/tilelink2/IntNodes.scala +++ b/src/main/scala/uncore/tilelink2/IntNodes.scala @@ -4,6 +4,7 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import scala.collection.mutable.ListBuffer import scala.math.max @@ -65,7 +66,7 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In override def labelI(ei: IntEdge) = ei.source.sources.map(_.range.size).sum.toString override def labelO(eo: IntEdge) = eo.source.sources.map(_.range.size).sum.toString - def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { + def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { (None, () => { // Cannot use bulk connect, because the widths could differ (bo zip bi) foreach { case (o, i) => i := o } @@ -100,7 +101,7 @@ case class IntBlindInputNode(num: Int) extends BlindInputNode(IntImp)(IntSourceP case class IntInternalOutputNode() extends InternalOutputNode(IntImp)(IntSinkPortParameters(Seq(IntSinkParameters()))) case class IntInternalInputNode(num: Int) extends InternalInputNode(IntImp)(IntSourcePortParameters(Seq(IntSourceParameters(num)))) -class IntXbar extends LazyModule +class IntXbar()(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode( numSourcePorts = 0 to 128, @@ -123,7 +124,7 @@ class IntXbar extends LazyModule } } -class IntXing extends LazyModule +class IntXing()(implicit p: Parameters) extends LazyModule { val intnode = IntIdentityNode() diff --git a/src/main/scala/uncore/tilelink2/Isolation.scala b/src/main/scala/uncore/tilelink2/Isolation.scala index 8bceeadf..bc3fcd44 100644 --- a/src/main/scala/uncore/tilelink2/Isolation.scala +++ b/src/main/scala/uncore/tilelink2/Isolation.scala @@ -4,11 +4,12 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import util.AsyncBundle // READ the comments in the TLIsolation object before you instantiate this module -class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt) extends LazyModule +class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implicit p: Parameters) extends LazyModule { val node = TLAsyncIdentityNode() @@ -76,7 +77,7 @@ object TLIsolation // fOut is applied to data flowing from client to manager // fIn is applied to data flowing from manager to client // **** WARNING: the isolation functions must bring the values to 0 **** - def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = { + def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = { val iso = LazyModule(new TLIsolation(fOut, fIn)) iso.node := x (iso.node, () => (iso.module.io.iso_out, iso.module.io.iso_in)) diff --git a/src/main/scala/uncore/tilelink2/Legacy.scala b/src/main/scala/uncore/tilelink2/Legacy.scala index 373f1e5d..34ef7bbd 100644 --- a/src/main/scala/uncore/tilelink2/Legacy.scala +++ b/src/main/scala/uncore/tilelink2/Legacy.scala @@ -8,19 +8,15 @@ import config._ import uncore.tilelink._ import uncore.constants._ -// Instantiate 'val p' before HasTileLinkParameters tries to use it -abstract class LegacyLazyModuleImp(module: LazyModule)(implicit val p: Parameters) - extends LazyModuleImp(module) with HasTileLinkParameters - -class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkParameters +class TLLegacy(implicit p: Parameters) extends LazyModule with HasTileLinkParameters { // TL legacy clients don't support anything fancy val node = TLClientNode(TLClientParameters( sourceId = IdRange(0, 1 << tlClientXactIdBits))) - lazy val module = new LegacyLazyModuleImp(this) { + lazy val module = new LazyModuleImp(this) with HasTileLinkParameters { val io = new Bundle { - val legacy = new ClientUncachedTileLinkIO()(p).flip + val legacy = new ClientUncachedTileLinkIO().flip val out = node.bundleOut } diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index 072ecb11..1e3a57c3 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -4,9 +4,31 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.{SourceInfo, SourceLine} +import config._ import diplomacy._ -class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: SourceInfo) extends LazyModule +case class TLMonitorArgs(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: SourceInfo, p: Parameters) + +abstract class TLMonitorBase(args: TLMonitorArgs) extends LazyModule()(args.p) +{ + implicit val sourceInfo = args.sourceInfo + + def legalize(bundle: TLBundleSnoop, edge: TLEdge): Unit + + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + + lazy val module = new LazyModuleImp(this) { + val io = new Bundle { + val in = args.gen().asInput + } + + code_insertion(io.in, edge()) + + legalize(io.in, args.edge()) + } +} + +class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) { def extra(implicit sourceInfo: SourceInfo) = { sourceInfo match { @@ -409,21 +431,9 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source inflight := (inflight | a_set) & ~d_clr } - def legalize(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) { - legalizeFormat (bundle, edge) - legalizeMultibeat (bundle, edge) + def legalize(bundle: TLBundleSnoop, edge: TLEdge) { + legalizeFormat (bundle, edge) + legalizeMultibeat (bundle, edge) legalizeSourceUnique(bundle, edge) } - - var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} - - lazy val module = new LazyModuleImp(this) { - val io = new Bundle { - val in = gen().asInput - } - - code_insertion(io.in, edge()) - - legalize(io.in, edge())(sourceInfo) - } } diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala index a78e3b0b..da879180 100644 --- a/src/main/scala/uncore/tilelink2/Nodes.scala +++ b/src/main/scala/uncore/tilelink2/Nodes.scala @@ -4,9 +4,14 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import scala.collection.mutable.ListBuffer +case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]] +case object TLFuzzReadyValid extends Field[Boolean] +case object TLCombinationalCheck extends Field[Boolean] + object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu) @@ -20,24 +25,16 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))) } - var emitMonitors = true - var stressTestDecoupled = false - var combinationalCheck = false - def colour = "#000000" // black override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString - def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { - val monitor = if (emitMonitors) { - Some(LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo))) - } else { - None - } + def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { + val monitor = p(TLMonitorBuilder)(TLMonitorArgs(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo, p)) (monitor, () => { bi <> bo monitor.foreach { _.module.io.in := TLBundleSnoop(bo) } - if (combinationalCheck) { + if (p(TLCombinationalCheck)) { // It is forbidden for valid to depend on ready in TL2 // If someone did that, then this will create a detectable combinational loop bo.a.ready := bi.a.ready && bo.a.valid @@ -46,7 +43,7 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL bi.d.ready := bo.d.ready && bi.d.valid bo.e.ready := bi.e.ready && bo.e.valid } - if (stressTestDecoupled) { + if (p(TLCombinationalCheck)) { // Randomly stall the transfers val allow = LFSRNoiseMaker(5) bi.a.valid := bo.a.valid && allow(0) @@ -132,7 +129,7 @@ case class TLInternalInputNode(portParams: TLClientPortParameters) extends Inter /** Synthesizeable unit tests */ import unittest._ -class TLInputNodeTest extends UnitTest(500000) { +class TLInputNodeTest()(implicit p: Parameters) extends UnitTest(500000) { class Acceptor extends LazyModule { val node = TLInputNode() val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff))) @@ -168,7 +165,7 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor override def labelI(ei: TLAsyncEdgeParameters) = ei.manager.depth.toString override def labelO(eo: TLAsyncEdgeParameters) = eo.manager.depth.toString - def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { + def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { (None, () => { bi <> bo }) } diff --git a/src/main/scala/uncore/tilelink2/RAMModel.scala b/src/main/scala/uncore/tilelink2/RAMModel.scala index 02c997ea..cee51935 100644 --- a/src/main/scala/uncore/tilelink2/RAMModel.scala +++ b/src/main/scala/uncore/tilelink2/RAMModel.scala @@ -3,6 +3,7 @@ package uncore.tilelink2 import Chisel._ +import config._ import diplomacy._ // We detect concurrent puts that put memory into an undefined state. @@ -20,7 +21,7 @@ import diplomacy._ // put, get, getAck, putAck => ok: detected by getAck (it sees busy>0) impossible for FIFO // If FIFO, the getAck should check data even if its validity was wiped -class TLRAMModel(log: String = "") extends LazyModule +class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule { val node = TLIdentityNode() diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index 42371e4e..4269380f 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -3,6 +3,7 @@ package uncore.tilelink2 import Chisel._ +import config._ import diplomacy._ import regmapper._ import scala.math.{min,max} @@ -79,21 +80,22 @@ object TLRegisterNode // register mapped device from a totally abstract register mapped device. // See GPIO.scala in this directory for an example -abstract class TLRegisterRouterBase(val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean) extends LazyModule +abstract class TLRegisterRouterBase(val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule { val node = TLRegisterNode(address, concurrency, beatBytes, undefZero, executable) val intnode = IntSourceNode(interrupts) } -case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle]) +case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])(implicit val p: Parameters) class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle { + implicit val p = arg.p val interrupts = arg.interrupts val in = arg.in } -class TLRegBundle[P](val params: P, arg: TLRegBundleArg) extends TLRegBundleBase(arg) +class TLRegBundle[P](val params: P, arg: TLRegBundleArg)(implicit p: Parameters) extends TLRegBundleBase(arg) class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase) extends LazyModuleImp(router) with HasRegMap @@ -107,7 +109,7 @@ class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, r class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp] (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) (bundleBuilder: TLRegBundleArg => B) - (moduleBuilder: (=> B, TLRegisterRouterBase) => M) + (moduleBuilder: (=> B, TLRegisterRouterBase) => M)(implicit p: Parameters) extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable) { require (isPow2(size)) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala index 35e8c3fa..fd527fcb 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala @@ -3,6 +3,7 @@ package uncore.tilelink2 import Chisel._ +import config._ import diplomacy._ import regmapper._ import unittest._ @@ -213,7 +214,7 @@ trait RRTest0Module extends HasRegMap regmap(RRTest0Map.map:_*) } -class RRTest0(address: BigInt) extends TLRegisterRouter(address, 0, 32, 0, 4)( +class RRTest0(address: BigInt)(implicit p: Parameters) extends TLRegisterRouter(address, 0, 32, 0, 4)( new TLRegBundle((), _) with RRTest0Bundle)( new TLRegModule((), _, _) with RRTest0Module) @@ -250,11 +251,11 @@ trait RRTest1Module extends Module with HasRegMap regmap(map:_*) } -class RRTest1(address: BigInt) extends TLRegisterRouter(address, 0, 32, 6, 4)( +class RRTest1(address: BigInt)(implicit p: Parameters) extends TLRegisterRouter(address, 0, 32, 6, 4)( new TLRegBundle((), _) with RRTest1Bundle)( new TLRegModule((), _, _) with RRTest1Module) -class FuzzRRTest0 extends LazyModule { +class FuzzRRTest0()(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val rrtr = LazyModule(new RRTest0(0x400)) @@ -265,11 +266,11 @@ class FuzzRRTest0 extends LazyModule { } } -class TLRR0Test extends UnitTest(timeout = 500000) { +class TLRR0Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) { io.finished := Module(LazyModule(new FuzzRRTest0).module).io.finished } -class FuzzRRTest1 extends LazyModule { +class FuzzRRTest1()(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val rrtr = LazyModule(new RRTest1(0x400)) @@ -280,7 +281,7 @@ class FuzzRRTest1 extends LazyModule { } } -class TLRR1Test extends UnitTest(timeout = 500000) { +class TLRR1Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) { io.finished := Module(LazyModule(new FuzzRRTest1).module).io.finished } diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala index 9f84eeee..86c2730b 100644 --- a/src/main/scala/uncore/tilelink2/SRAM.scala +++ b/src/main/scala/uncore/tilelink2/SRAM.scala @@ -3,9 +3,10 @@ package uncore.tilelink2 import Chisel._ +import config._ import diplomacy._ -class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule +class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule { val node = TLManagerNode(TLManagerPortParameters( Seq(TLManagerParameters( @@ -84,7 +85,7 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) /** Synthesizeable unit testing */ import unittest._ -class TLRAMSimple(ramBeatBytes: Int) extends LazyModule { +class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val model = LazyModule(new TLRAMModel) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) @@ -97,6 +98,6 @@ class TLRAMSimple(ramBeatBytes: Int) extends LazyModule { } } -class TLRAMSimpleTest(ramBeatBytes: Int) extends UnitTest(timeout = 500000) { +class TLRAMSimpleTest(ramBeatBytes: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) { io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes)).module).io.finished } diff --git a/src/main/scala/uncore/tilelink2/SourceShrinker.scala b/src/main/scala/uncore/tilelink2/SourceShrinker.scala index 3c0aa02e..d4948bc4 100644 --- a/src/main/scala/uncore/tilelink2/SourceShrinker.scala +++ b/src/main/scala/uncore/tilelink2/SourceShrinker.scala @@ -4,10 +4,11 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import scala.math.{min,max} -class TLSourceShrinker(maxInFlight: Int) extends LazyModule +class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyModule { require (maxInFlight > 0) @@ -78,7 +79,7 @@ class TLSourceShrinker(maxInFlight: Int) extends LazyModule object TLSourceShrinker { // applied to the TL source node; y.node := TLSourceShrinker(n)(x.node) - def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = { + def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val shrinker = LazyModule(new TLSourceShrinker(maxInFlight)) shrinker.node := x shrinker.node diff --git a/src/main/scala/uncore/tilelink2/ToAHB.scala b/src/main/scala/uncore/tilelink2/ToAHB.scala new file mode 100644 index 00000000..bdc8b454 --- /dev/null +++ b/src/main/scala/uncore/tilelink2/ToAHB.scala @@ -0,0 +1,141 @@ +// See LICENSE.SiFive for license details. + +package uncore.tilelink2 + +import Chisel._ +import chisel3.internal.sourceinfo.SourceInfo +import config._ +import diplomacy._ +import util.PositionalMultiQueue +import uncore.ahb._ +import scala.math.{min, max} +import AHBParameters._ + +case class TLToAHBNode() extends MixedNode(TLImp, AHBImp)( + dFn = { case (1, Seq(TLClientPortParameters(clients, unsafeAtomics, minLatency))) => + val masters = clients.map { case c => AHBMasterParameters(nodePath = c.nodePath) } + Seq(AHBMasterPortParameters(masters)) + }, + uFn = { case (1, Seq(AHBSlavePortParameters(slaves, beatBytes))) => + val managers = slaves.map { case s => + TLManagerParameters( + address = s.address, + regionType = s.regionType, + executable = s.executable, + nodePath = s.nodePath, + supportsGet = s.supportsRead, + supportsPutFull = s.supportsWrite, // but not PutPartial + fifoId = Some(0)) // a common FIFO domain + } + Seq(TLManagerPortParameters(managers, beatBytes, 1, 1)) + }, + numPO = 1 to 1, + numPI = 1 to 1) + +class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends LazyModule +{ + val node = TLToAHBNode() + + lazy val module = new LazyModuleImp(this) { + val io = new Bundle { + val in = node.bundleIn + val out = node.bundleOut + } + + val in = io.in(0) + val out = io.out(0) + val edgeIn = node.edgesIn(0) + val edgeOut = node.edgesOut(0) + val beatBytes = edgeOut.slave.beatBytes + val maxTransfer = edgeOut.slave.maxTransfer + val lgMax = log2Ceil(maxTransfer) + val lgBytes = log2Ceil(beatBytes) + + // AHB has no cache coherence + in.b.valid := Bool(false) + in.c.ready := Bool(true) + in.e.ready := Bool(true) + + // We need a skidpad to capture D output: + // We cannot know if the D response will be accepted until we have + // presented it on D as valid. We also can't back-pressure AHB in the + // data phase. Therefore, we must have enough space to save the data + // phase result. Whenever we have a queued response, we can not allow + // AHB to present new responses, so we must quash the address phase. + val d = Wire(in.d) + in.d <> Queue(d, 1, flow = true) + val a_quash = in.d.valid && !in.d.ready + + // Record what is coming out in d_phase + val d_valid = RegInit(Bool(false)) + val d_hasData = Reg(Bool()) + val d_error = Reg(Bool()) + val d_addr_lo = Reg(UInt(width = lgBytes)) + val d_source = Reg(UInt()) + val d_size = Reg(UInt()) + + when (out.hreadyout) { d_error := d_error || out.hresp } + when (d.fire()) { d_valid := Bool(false) } + + d.valid := d_valid && out.hreadyout + d.bits := edgeIn.AccessAck(d_addr_lo, UInt(0), d_source, d_size, out.hrdata, out.hresp || d_error) + d.bits.opcode := Mux(d_hasData, TLMessages.AccessAckData, TLMessages.AccessAck) + + // We need an irrevocable input for AHB to stall on read bursts + // We also need the values to NOT change when valid goes low => 1 entry only + val a = Queue(in.a, 1, flow = combinational, pipe = !combinational) + val a_valid = a.valid && !a_quash + + // This is lot like TLEdge.firstlast, but counts beats also for single-beat TL types + val a_size = edgeIn.size(a.bits) + val a_beats1 = UIntToOH1(a_size, lgMax) >> lgBytes + val a_counter = RegInit(UInt(0, width = log2Up(maxTransfer/beatBytes))) + val a_counter1 = a_counter - UInt(1) + val a_first = a_counter === UInt(0) + val a_last = a_counter === UInt(1) || a_beats1 === UInt(0) + val a_offset = (a_beats1 & ~a_counter1) << lgBytes + val a_hasData = edgeIn.hasData(a.bits) + + // Expand no-data A-channel requests into multiple beats + a.ready := (a_hasData || a_last) && out.hreadyout && !a_quash + when (a_valid && out.hreadyout) { + a_counter := Mux(a_first, a_beats1, a_counter1) + d_valid := !a_hasData || a_last + // Record what will be in the data phase + when (a_first) { + d_hasData := !a_hasData + d_error := Bool(false) + d_addr_lo := a.bits.address + d_source := a.bits.source + d_size := a.bits.size + } + } + + // Transform TL size into AHB hsize+hburst + val a_size_bits = a_size.getWidth + val a_sizeDelta = Cat(UInt(0, width = 1), a_size) - UInt(lgBytes+1) + val a_singleBeat = a_sizeDelta(a_size_bits) + val a_logBeats1 = a_sizeDelta(a_size_bits-1, 0) + + out.hmastlock := Bool(false) // for now + out.htrans := Mux(a_valid, Mux(a_first, TRANS_NONSEQ, TRANS_SEQ), Mux(a_first, TRANS_IDLE, TRANS_BUSY)) + out.hsel := Bool(true) + out.hready := out.hreadyout + out.hwrite := a_hasData + out.haddr := a.bits.address | a_offset + out.hsize := Mux(a_singleBeat, a.bits.size, UInt(lgBytes)) + out.hburst := Mux(a_singleBeat, BURST_SINGLE, (a_logBeats1<<1) | UInt(1)) + out.hprot := PROT_DEFAULT + out.hwdata := RegEnable(a.bits.data, a.fire()) + } +} + +object TLToAHB +{ + // applied to the TL source node; y.node := TLToAHB()(x.node) + def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = { + val axi4 = LazyModule(new TLToAHB(combinational)) + axi4.node := x + axi4.node + } +} diff --git a/src/main/scala/uncore/tilelink2/ToAXI4.scala b/src/main/scala/uncore/tilelink2/ToAXI4.scala index 3aefa307..53fec766 100644 --- a/src/main/scala/uncore/tilelink2/ToAXI4.scala +++ b/src/main/scala/uncore/tilelink2/ToAXI4.scala @@ -4,6 +4,7 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import util.PositionalMultiQueue import uncore.axi4._ @@ -35,7 +36,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)( numPO = 1 to 1, numPI = 1 to 1) -class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule +class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule { val node = TLToAXI4Node(idBits) @@ -229,7 +230,7 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule object TLToAXI4 { // applied to the TL source node; y.node := TLToAXI4(idBits)(x.node) - def apply(idBits: Int, combinational: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = { + def apply(idBits: Int, combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = { val axi4 = LazyModule(new TLToAXI4(idBits, combinational)) axi4.node := x axi4.node diff --git a/src/main/scala/uncore/tilelink2/WidthWidget.scala b/src/main/scala/uncore/tilelink2/WidthWidget.scala index bde1f830..7a8aa01f 100644 --- a/src/main/scala/uncore/tilelink2/WidthWidget.scala +++ b/src/main/scala/uncore/tilelink2/WidthWidget.scala @@ -4,11 +4,12 @@ package uncore.tilelink2 import Chisel._ import chisel3.internal.sourceinfo.SourceInfo +import config._ import diplomacy._ import scala.math.{min,max} // innBeatBytes => the new client-facing bus width -class TLWidthWidget(innerBeatBytes: Int) extends LazyModule +class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { val node = TLAdapterNode( clientFn = { case Seq(c) => c }, @@ -166,7 +167,7 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule object TLWidthWidget { // applied to the TL source node; y.node := WidthWidget(x.node, 16) - def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = { + def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node := x widget.node @@ -176,7 +177,7 @@ object TLWidthWidget /** Synthesizeable unit tests */ import unittest._ -class TLRAMWidthWidget(first: Int, second: Int) extends LazyModule { +class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val model = LazyModule(new TLRAMModel) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) @@ -193,6 +194,6 @@ class TLRAMWidthWidget(first: Int, second: Int) extends LazyModule { } } -class TLRAMWidthWidgetTest(little: Int, big: Int) extends UnitTest(timeout = 500000) { +class TLRAMWidthWidgetTest(little: Int, big: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) { io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big)).module).io.finished } diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala index 401e9064..6e6b8fb8 100644 --- a/src/main/scala/uncore/tilelink2/Xbar.scala +++ b/src/main/scala/uncore/tilelink2/Xbar.scala @@ -3,9 +3,10 @@ package uncore.tilelink2 import Chisel._ +import config._ import diplomacy._ -class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends LazyModule +class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p: Parameters) extends LazyModule { def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId)) @@ -184,7 +185,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends Lazy /** Synthesizeable unit tests */ import unittest._ -class TLRAMXbar(nManagers: Int) extends LazyModule { +class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val model = LazyModule(new TLRAMModel) val xbar = LazyModule(new TLXbar) @@ -201,11 +202,11 @@ class TLRAMXbar(nManagers: Int) extends LazyModule { } } -class TLRAMXbarTest(nManagers: Int) extends UnitTest(timeout = 500000) { +class TLRAMXbarTest(nManagers: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) { io.finished := Module(LazyModule(new TLRAMXbar(nManagers)).module).io.finished } -class TLMulticlientXbar(nManagers: Int, nClients: Int) extends LazyModule { +class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => @@ -224,6 +225,6 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int) extends LazyModule { } } -class TLMulticlientXbarTest(nManagers: Int, nClients: Int) extends UnitTest(timeout = 5000000) { +class TLMulticlientXbarTest(nManagers: Int, nClients: Int)(implicit p: Parameters) extends UnitTest(timeout = 5000000) { io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients)).module).io.finished } diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala index f46e9902..ab714be3 100644 --- a/src/main/scala/unittest/Configs.scala +++ b/src/main/scala/unittest/Configs.scala @@ -25,14 +25,17 @@ class JunctionsUnitTestConfig extends Config(new WithJunctionsUnitTests ++ new B class WithUncoreUnitTests extends Config( (pname, site, here) => pname match { case uncore.tilelink.TLId => "L1toL2" - case UnitTests => (p: Parameters) => Seq( - Module(new uncore.devices.ROMSlaveTest()(p)), - Module(new uncore.devices.TileLinkRAMTest()(p)), - Module(new uncore.converters.TileLinkWidthAdapterTest()(p)), - Module(new uncore.tilelink2.TLFuzzRAMTest), - Module(new uncore.axi4.AXI4LiteFuzzRAMTest), - Module(new uncore.axi4.AXI4FullFuzzRAMTest), - Module(new uncore.axi4.AXI4BridgeTest)) + case UnitTests => (q: Parameters) => { + implicit val p = q + Seq( + Module(new uncore.devices.ROMSlaveTest()), + Module(new uncore.devices.TileLinkRAMTest()), + Module(new uncore.converters.TileLinkWidthAdapterTest()), + Module(new uncore.tilelink2.TLFuzzRAMTest), + Module(new uncore.ahb.AHBBridgeTest), + Module(new uncore.axi4.AXI4LiteFuzzRAMTest), + Module(new uncore.axi4.AXI4FullFuzzRAMTest), + Module(new uncore.axi4.AXI4BridgeTest)) } case _ => throw new CDEMatchError } ) @@ -41,7 +44,8 @@ class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new BaseCon class WithTLSimpleUnitTests extends Config( (pname, site, here) => pname match { - case UnitTests => (p: Parameters) => { + case UnitTests => (q: Parameters) => { + implicit val p = q Seq( Module(new uncore.tilelink2.TLRAMSimpleTest(1)), Module(new uncore.tilelink2.TLRAMSimpleTest(4)), @@ -53,7 +57,9 @@ class WithTLSimpleUnitTests extends Config( class WithTLWidthUnitTests extends Config( (pname, site, here) => pname match { - case UnitTests => (p: Parameters) => { Seq( + case UnitTests => (q: Parameters) => { + implicit val p = q + Seq( Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256)), Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64)), Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16)), @@ -64,7 +70,9 @@ class WithTLWidthUnitTests extends Config( class WithTLXbarUnitTests extends Config( (pname, site, here) => pname match { - case UnitTests => (p: Parameters) => { Seq( + case UnitTests => (q: Parameters) => { + implicit val p = q + Seq( Module(new uncore.tilelink2.TLRAMXbarTest(1)), Module(new uncore.tilelink2.TLRAMXbarTest(2)), Module(new uncore.tilelink2.TLRAMXbarTest(8)), diff --git a/src/main/scala/util/ConfigUtils.scala b/src/main/scala/util/ConfigUtils.scala deleted file mode 100644 index ff5d42ce..00000000 --- a/src/main/scala/util/ConfigUtils.scala +++ /dev/null @@ -1,11 +0,0 @@ -// See LICENSE.Berkeley for license details. - -package util - -import scala.math.max - -object ConfigUtils { - def max_int(values: Int*): Int = { - values.reduce((a, b) => max(a, b)) - } -} diff --git a/src/main/scala/util/GenericParameterizedBundle.scala b/src/main/scala/util/GenericParameterizedBundle.scala index 2b0104d1..bed000e5 100644 --- a/src/main/scala/util/GenericParameterizedBundle.scala +++ b/src/main/scala/util/GenericParameterizedBundle.scala @@ -4,7 +4,7 @@ package util import Chisel._ -abstract class GenericParameterizedBundle[T <: Object](val params: T) extends Bundle +abstract class GenericParameterizedBundle[+T <: Object](val params: T) extends Bundle { override def cloneType = { try {