riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha).

Browse Source
This commit is contained in:
Stephen Twigg
2014-02-14 10:12:09 -08:00
parent 6808245bb5
commit 755293d785
1 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/RocketChip.scala
View File

@@ -255,9 +255,11 @@ class Top extends Module {
val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val vic = ICacheConfig(128, 1)
val hc = hwacha.HwachaConfiguration(vic, 8, 256, ndtlb = 8, nptlb = 2)
val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU)
fpu = HAS_FPU
//,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
)
val io = new VLSITopIO(HTIF_WIDTH)