riscv/rocket-chip
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some fixes and cleanup to stateless bridge

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This commit is contained in:
Howard Mao
2016-07-21 18:33:46 -07:00
parent c31c650def
commit 75347eed56
4 changed files with 30 additions and 8 deletions
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12
src/main/scala/TestConfigs.scala
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@ -19,7 +19,9 @@ class WithGroundTest extends Config(
(pname, site, here) => pname match {
case TLKey("L1toL2") =>
TileLinkParameters(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1)
new MEICoherence(site(L2DirectoryRepresentation)) else
new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NUncachedTileLinkPorts),
@ -211,12 +213,16 @@ class ComparatorL2Config extends Config(
new WithL2Cache ++ new ComparatorConfig)
class ComparatorBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new ComparatorConfig)
class ComparatorStatelessConfig extends Config(
new WithStatelessBridge ++ new ComparatorConfig)
class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
class MemtestL2Config extends Config(
new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
new WithL2Cache ++ new MemtestConfig)
class MemtestBufferlessConfig extends Config(
new WithMemtest ++ new WithBufferlessBroadcastHub ++ new GroundTestConfig)
new WithBufferlessBroadcastHub ++ new MemtestConfig)
class MemtestStatelessConfig extends Config(
new WithNGenerators(0, 1) ++ new WithStatelessBridge ++ new MemtestConfig)
// Test ALL the things
class FancyMemtestConfig extends Config(
new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++