diff --git a/regression/Makefile b/regression/Makefile
index 38cbfd8a..3444730c 100644
--- a/regression/Makefile
+++ b/regression/Makefile
@@ -48,9 +48,9 @@ CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig RoccExampleConfig
 endif
 
 ifeq ($(SUITE),GroundtestSuite)
-CONFIGS=MemtestConfig MemtestBufferlessConfig FancyMemtestConfig \
+CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \
 	BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
-	ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config \
+	ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig \
 	UnitTestConfig
 endif
 
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index aa27f7e5..f0447161 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -256,7 +256,7 @@ class BaseConfig extends Config (
           dataBits = site(XLen))
       case TLKey("L1toL2") =>
         TileLinkParameters(
-          coherencePolicy = (if (site(NTiles) == 1)
+          coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1)
             new MEICoherence(site(L2DirectoryRepresentation)) else
               new MESICoherence(site(L2DirectoryRepresentation))),
           nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
@@ -381,12 +381,28 @@ class WithBufferlessBroadcastHub extends Config(
         case OuterTLId => "L2toMC" })))
   })
 
+/**
+ * WARNING!!! IGNORE AT YOUR OWN PERIL!!!
+ *
+ * There is a very restrictive set of conditions under which the stateless
+ * bridge will function properly. There can only be a single tile. This tile
+ * MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
+ * uncached channel capable of writes (i.e. a RoCC accelerator).
+ *
+ * This is because the stateless bridge CANNOT generate probes, so if your
+ * system depends on coherence between channels in any way,
+ * DO NOT use this configuration.
+ */
 class WithStatelessBridge extends Config (
-  (pname, site, here) => pname match {
+  topDefinitions = (pname, site, here) => pname match {
     case BuildL2CoherenceManager => (id: Int, p: Parameters) =>
       Module(new ManagerToClientStatelessBridge()(p.alterPartial({
         case InnerTLId => "L1toL2"
         case OuterTLId => "L2toMC" })))
+  },
+  knobValues = {
+    case "L1D_MSHRS" => 0
+    case _ => throw new CDEMatchError
   }
 )
 
diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala
index d733ff4d..0681e30a 100644
--- a/src/main/scala/TestConfigs.scala
+++ b/src/main/scala/TestConfigs.scala
@@ -19,7 +19,9 @@ class WithGroundTest extends Config(
   (pname, site, here) => pname match {
     case TLKey("L1toL2") =>
       TileLinkParameters(
-        coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
+        coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1)
+          new MEICoherence(site(L2DirectoryRepresentation)) else
+            new MESICoherence(site(L2DirectoryRepresentation))),
         nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
         nCachingClients = site(NCachedTileLinkPorts),
         nCachelessClients = site(NUncachedTileLinkPorts),
@@ -211,12 +213,16 @@ class ComparatorL2Config extends Config(
   new WithL2Cache ++ new ComparatorConfig)
 class ComparatorBufferlessConfig extends Config(
   new WithBufferlessBroadcastHub ++ new ComparatorConfig)
+class ComparatorStatelessConfig extends Config(
+  new WithStatelessBridge ++ new ComparatorConfig)
 
 class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
 class MemtestL2Config extends Config(
-  new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
+  new WithL2Cache ++ new MemtestConfig)
 class MemtestBufferlessConfig extends Config(
-  new WithMemtest ++ new WithBufferlessBroadcastHub ++ new GroundTestConfig)
+  new WithBufferlessBroadcastHub ++ new MemtestConfig)
+class MemtestStatelessConfig extends Config(
+  new WithNGenerators(0, 1) ++ new WithStatelessBridge ++ new MemtestConfig)
 // Test ALL the things
 class FancyMemtestConfig extends Config(
   new WithNGenerators(1, 2) ++ new WithNCores(2) ++ new WithMemtest ++
diff --git a/uncore b/uncore
index b4092a6f..384655ea 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit b4092a6ff8021b0e57ab5ce8c11ef6a6dafec1fb
+Subproject commit 384655ea7b09f9d14014737a2cba1a9489151900