riscv/rocket-chip
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some fixes and cleanup to stateless bridge

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This commit is contained in:
Howard Mao
2016-07-21 18:33:46 -07:00
parent c31c650def
commit 75347eed56
4 changed files with 30 additions and 8 deletions
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regression/Makefile
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@ -48,9 +48,9 @@ CONFIGS=DefaultConfig DefaultL2Config DefaultBufferlessConfig RoccExampleConfig
endif
ifeq ($(SUITE),GroundtestSuite)
CONFIGS=MemtestConfig MemtestBufferlessConfig FancyMemtestConfig \
CONFIGS=MemtestConfig MemtestBufferlessConfig MemtestStatelessConfig FancyMemtestConfig \
BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config \
ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig \
UnitTestConfig
endif