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Refactor Tile to use cake pattern (#502)

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* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
2017-01-16 18:24:08 -08:00
committed by GitHub
parent 622e311962
commit 74b6a8d02b
32 changed files with 686 additions and 519 deletions
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2
src/main/scala/uncore/converters/Ahb.scala
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@ -398,7 +398,7 @@ class AHBBridge(supportAtomics: Boolean = true)(implicit val p: Parameters) exte
// Hasti and TileLink widths must agree at this point in the topology
require (tlDataBits == hastiDataBits)
require (p(PAddrBits) == hastiAddrBits)
require (p(rocket.PAddrBits) == hastiAddrBits)
// AHB does not permit bursts to cross a 1KB boundary
require (tlDataBits * tlDataBeats <= 1024*8)

2
src/main/scala/uncore/converters/Tilelink.scala
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@ -5,7 +5,7 @@ package uncore.converters
import Chisel._
import util.{ReorderQueue, DecoupledHelper}
import junctions.PAddrBits
import rocket.PAddrBits
import uncore.tilelink._
import uncore.util._
import uncore.constants._