Refactor Tile to use cake pattern (#502)

* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests

src/main/scala/uncore/agents/Agents.scala

@@ -5,7 +5,7 @@ package uncore.agents
 
 import Chisel._
 import config._
-import junctions.PAddrBits
+import rocket.PAddrBits
 import uncore.tilelink._
 import uncore.converters._
 import uncore.coherence._

src/main/scala/uncore/agents/L2Cache.scala

@@ -5,7 +5,7 @@ package uncore.agents
 
 import Chisel._
 import scala.reflect.ClassTag
-import junctions.PAddrBits
+import rocket.PAddrBits
 import uncore.coherence._
 import uncore.tilelink._
 import uncore.constants._

src/main/scala/uncore/converters/Ahb.scala

@@ -398,7 +398,7 @@ class AHBBridge(supportAtomics: Boolean = true)(implicit val p: Parameters) exte
   
   // Hasti and TileLink widths must agree at this point in the topology
   require (tlDataBits == hastiDataBits)
-  require (p(PAddrBits) == hastiAddrBits)
+  require (p(rocket.PAddrBits) == hastiAddrBits)
   
   // AHB does not permit bursts to cross a 1KB boundary
   require (tlDataBits * tlDataBeats <= 1024*8)

src/main/scala/uncore/converters/Tilelink.scala

@@ -5,7 +5,7 @@ package uncore.converters
 
 import Chisel._
 import util.{ReorderQueue, DecoupledHelper}
-import junctions.PAddrBits
+import rocket.PAddrBits
 import uncore.tilelink._
 import uncore.util._
 import uncore.constants._

src/main/scala/uncore/tilelink/Definitions.scala

@@ -65,7 +65,7 @@ trait HasTileLinkParameters {
   val tlMaxManagerXacts = tlExternal.maxManagerXacts
   val tlClientXactIdBits = log2Up(tlMaxClientXacts*tlMaxClientsPerPort)
   val tlManagerXactIdBits = log2Up(tlMaxManagerXacts)
-  val tlBlockAddrBits = p(PAddrBits) - p(CacheBlockOffsetBits)
+  val tlBlockAddrBits = p(rocket.PAddrBits) - p(CacheBlockOffsetBits)
   val tlDataBeats = tlExternal.dataBeats
   val tlDataBits = tlExternal.dataBitsPerBeat
   val tlDataBytes = tlDataBits/8

src/main/scala/uncore/util/Cache.scala

@@ -5,7 +5,7 @@ package uncore.util
 
 import Chisel._
 import config.{Parameters, Field}
-import junctions.PAddrBits
+import rocket.PAddrBits
 import util.ParameterizedBundle
 import uncore.constants._