riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Refactor Tile to use cake pattern (#502)

Browse Source 
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
2017-01-16 18:24:08 -08:00
committed by GitHub
parent 622e311962
commit 74b6a8d02b
32 changed files with 686 additions and 519 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocket/csr.scala
View File

@ -155,7 +155,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
val time = UInt(OUTPUT, xLen)
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
val rocc = new RoCCInterface().flip
val rocc_interrupt = Bool(INPUT)
val interrupt = Bool(OUTPUT)
val interrupt_cause = UInt(OUTPUT, xLen)
val bp = Vec(nBreakpoints, new BP).asOutput
@ -252,7 +252,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val reg_hpmcounter = reg_hpmevent.map(e => WideCounter(64, ((UInt(0) +: io.events): Seq[UInt])(e)))
val mip = Wire(init=reg_mip)
mip.rocc := io.rocc.interrupt
mip.rocc := io.rocc_interrupt
val read_mip = mip.asUInt & supported_interrupts
val pending_interrupts = read_mip & reg_mie