riscv/rocket-chip
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Refactor Tile to use cake pattern (#502)

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* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
2017-01-16 18:24:08 -08:00
committed by GitHub
parent 622e311962
commit 74b6a8d02b
32 changed files with 686 additions and 519 deletions
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31
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -101,3 +101,34 @@ class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
tl_in.e.ready := Bool(true)
}
}
/** Mix-ins for constructing tiles that have optional scratchpads */
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
val module: CanHaveScratchpadModule
val slaveNode = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode())
val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams)))
(slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
val finalNode = frontend.node.edgesOut(0).manager.managers.find(_.nodePath.last == s.node)
require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
finalNode.get.address(0)
}
nDCachePorts += 1 // core TODO dcachePorts += () => module.io.dmem ??
}
trait CanHaveScratchpadBundle extends HasHellaCacheBundle with HasICacheFrontendBundle {
val outer: CanHaveScratchpad
val slave = outer.slaveNode.map(_.bundleIn)
}
trait CanHaveScratchpadModule extends HasHellaCacheModule with HasICacheFrontendModule {
val outer: CanHaveScratchpad
val io: CanHaveScratchpadBundle
outer.scratch.foreach { lm => dcachePorts += lm.module.io.dmem }
}