Refactor Tile to use cake pattern (#502)
* [rocket] Refactor Tile into cake pattern with traits * [rocket] cacheDataBits &etc in HasCoreParameters * [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters * [rocket] frontend and icache now diplomatic * [rocket] file name capitalization * [rocket] re-add hook for inserting externally-defined Cores * [rocket] add FPUCoreIO * [groundtest] move TL1 Config instances to where they are used * [unittest] remove legacy unit tests * [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
GitHub
234
src/main/scala/rocket/PTW.scala
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234
src/main/scala/rocket/PTW.scala
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// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import config._
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import uncore.constants._
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import uncore.util.PseudoLRU
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import util._
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import Chisel.ImplicitConversions._
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import scala.collection.mutable.ListBuffer
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class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
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val prv = Bits(width = 2)
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val pum = Bool()
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val mxr = Bool()
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val addr = UInt(width = vpnBits)
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val store = Bool()
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val fetch = Bool()
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}
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class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
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val pte = new PTE
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}
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class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Decoupled(new PTWReq)
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val resp = Valid(new PTWResp).flip
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val ptbr = new PTBR().asInput
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val invalidate = Bool(INPUT)
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val status = new MStatus().asInput
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}
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class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) {
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val ptbr = new PTBR().asInput
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val invalidate = Bool(INPUT)
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val status = new MStatus().asInput
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}
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class PTE(implicit p: Parameters) extends CoreBundle()(p) {
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val reserved_for_hardware = Bits(width = 16)
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val ppn = UInt(width = 38)
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val reserved_for_software = Bits(width = 2)
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val d = Bool()
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val a = Bool()
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val g = Bool()
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val u = Bool()
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val x = Bool()
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val w = Bool()
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val r = Bool()
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val v = Bool()
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def table(dummy: Int = 0) = v && !r && !w && !x
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def leaf(dummy: Int = 0) = v && (r || (x && !w))
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def ur(dummy: Int = 0) = sr() && u
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def uw(dummy: Int = 0) = sw() && u
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def ux(dummy: Int = 0) = sx() && u
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def sr(dummy: Int = 0) = leaf() && r
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def sw(dummy: Int = 0) = leaf() && w
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def sx(dummy: Int = 0) = leaf() && x
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def access_ok(req: PTWReq) = {
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val perm_ok = Mux(req.fetch, x, Mux(req.store, w, r || (x && req.mxr)))
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val priv_ok = Mux(u, !req.pum, req.prv(0))
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leaf() && priv_ok && perm_ok
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}
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}
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class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestor = Vec(n, new TLBPTWIO).flip
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val mem = new HellaCacheIO
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val dpath = new DatapathPTWIO
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}
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require(usingAtomics, "PTW requires atomic memory operations")
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val s_ready :: s_req :: s_wait1 :: s_wait2 :: s_set_dirty :: s_wait1_dirty :: s_wait2_dirty :: s_done :: Nil = Enum(UInt(), 8)
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val state = Reg(init=s_ready)
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val count = Reg(UInt(width = log2Up(pgLevels)))
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val s1_kill = Reg(next = Bool(false))
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val r_req = Reg(new PTWReq)
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val r_req_dest = Reg(Bits())
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val r_pte = Reg(new PTE)
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val vpn_idxs = (0 until pgLevels).map(i => (r_req.addr >> (pgLevels-i-1)*pgLevelBits)(pgLevelBits-1,0))
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val vpn_idx = vpn_idxs(count)
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val arb = Module(new RRArbiter(new PTWReq, n))
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arb.io.in <> io.requestor.map(_.req)
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arb.io.out.ready := state === s_ready
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val pte = {
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val tmp = new PTE().fromBits(io.mem.resp.bits.data)
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val res = Wire(init = new PTE().fromBits(io.mem.resp.bits.data))
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res.ppn := tmp.ppn(ppnBits-1, 0)
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when ((tmp.ppn >> ppnBits) =/= 0) { res.v := false }
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res
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}
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val pte_addr = Cat(r_pte.ppn, vpn_idx) << log2Ceil(xLen/8)
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when (arb.io.out.fire()) {
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r_req := arb.io.out.bits
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r_req_dest := arb.io.chosen
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r_pte.ppn := io.dpath.ptbr.ppn
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}
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val (pte_cache_hit, pte_cache_data) = {
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val size = 1 << log2Up(pgLevels * 2)
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val plru = new PseudoLRU(size)
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val valid = Reg(init = UInt(0, size))
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val tags = Reg(Vec(size, UInt(width = paddrBits)))
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val data = Reg(Vec(size, UInt(width = ppnBits)))
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val hits = tags.map(_ === pte_addr).asUInt & valid
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val hit = hits.orR
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when (io.mem.resp.valid && pte.table() && !hit) {
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val r = Mux(valid.andR, plru.replace, PriorityEncoder(~valid))
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valid := valid | UIntToOH(r)
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tags(r) := pte_addr
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data(r) := pte.ppn
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}
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when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
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when (io.dpath.invalidate) { valid := 0 }
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(hit && count < pgLevels-1, Mux1H(hits, data))
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}
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val pte_wdata = Wire(init=new PTE().fromBits(0))
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pte_wdata.a := true
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pte_wdata.d := r_req.store
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io.mem.req.valid := state.isOneOf(s_req, s_set_dirty)
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io.mem.req.bits.phys := Bool(true)
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io.mem.req.bits.cmd := Mux(state === s_set_dirty, M_XA_OR, M_XRD)
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io.mem.req.bits.typ := log2Ceil(xLen/8)
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io.mem.req.bits.addr := pte_addr
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io.mem.s1_data := pte_wdata.asUInt
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io.mem.s1_kill := s1_kill
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io.mem.invalidate_lr := Bool(false)
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val resp_ppns = (0 until pgLevels-1).map(i => Cat(pte_addr >> (pgIdxBits + pgLevelBits*(pgLevels-i-1)), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ (pte_addr >> pgIdxBits)
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for (i <- 0 until io.requestor.size) {
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io.requestor(i).resp.valid := state === s_done && (r_req_dest === i)
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io.requestor(i).resp.bits.pte := r_pte
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io.requestor(i).resp.bits.pte.ppn := resp_ppns(count)
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io.requestor(i).ptbr := io.dpath.ptbr
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io.requestor(i).invalidate := io.dpath.invalidate
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io.requestor(i).status := io.dpath.status
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}
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// control state machine
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switch (state) {
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is (s_ready) {
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when (arb.io.out.valid) {
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state := s_req
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}
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count := UInt(0)
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}
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is (s_req) {
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when (pte_cache_hit) {
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s1_kill := true
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state := s_req
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count := count + 1
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r_pte.ppn := pte_cache_data
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}.elsewhen (io.mem.req.ready) {
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state := s_wait1
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}
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}
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is (s_wait1) {
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state := s_wait2
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when (io.mem.xcpt.pf.ld) {
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r_pte.v := false
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state := s_done
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}
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}
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is (s_wait2) {
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when (io.mem.s2_nack) {
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state := s_req
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}
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when (io.mem.resp.valid) {
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state := s_done
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when (pte.access_ok(r_req) && (!pte.a || (r_req.store && !pte.d))) {
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state := s_set_dirty
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}.otherwise {
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r_pte := pte
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}
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when (pte.table() && count < pgLevels-1) {
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state := s_req
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count := count + 1
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}
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}
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}
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is (s_set_dirty) {
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when (io.mem.req.ready) {
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state := s_wait1_dirty
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}
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}
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is (s_wait1_dirty) {
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state := s_wait2_dirty
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when (io.mem.xcpt.pf.st) {
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r_pte.v := false
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state := s_done
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}
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}
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is (s_wait2_dirty) {
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when (io.mem.s2_nack) {
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state := s_set_dirty
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}
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when (io.mem.resp.valid) {
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state := s_req
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}
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}
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is (s_done) {
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state := s_ready
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}
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}
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}
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/** Mix-ins for constructing tiles that might have a PTW */
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trait CanHavePTW extends HasHellaCache {
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implicit val p: Parameters
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val module: CanHavePTWModule
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var nPTWPorts = 1
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}
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trait CanHavePTWModule extends HasHellaCacheModule {
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val outer: CanHavePTW
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val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
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val ptwOpt = if (outer.p(UseVM)) { Some(Module(new PTW(outer.nPTWPorts)(outer.p))) } else None
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ptwOpt foreach { ptw => dcachePorts += ptw.io.mem }
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}
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