riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Refactor Tile to use cake pattern (#502)

Browse Source 
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
2017-01-16 18:24:08 -08:00
committed by GitHub
parent 622e311962
commit 74b6a8d02b
32 changed files with 686 additions and 519 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/ICache.scala
View File

@ -15,7 +15,7 @@ import Chisel.ImplicitConversions._
trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
val cacheBlockBytes = p(CacheBlockBytes)
val lgCacheBlockBytes = log2Up(cacheBlockBytes)
val cacheDataBits = p(TLCacheEdge).bundle.dataBits
val cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits
val cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits
val refillCycles = cacheDataBeats
}