Refactor Tile to use cake pattern (#502)

* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests

src/main/scala/rocket/HellaCache.scala

@@ -5,12 +5,13 @@ package rocket
 
 import Chisel._
 import config.{Parameters, Field}
+import coreplex._
 import diplomacy._
+import uncore.constants._
 import uncore.tilelink2._
 import uncore.util._
-import uncore.constants._
-import uncore.tilelink.{TLKey, TLId}
 import util.ParameterizedBundle
+import scala.collection.mutable.ListBuffer
 
 case class DCacheConfig(
   nMSHRs: Int = 1,
@@ -146,3 +147,26 @@ object HellaCache {
     else LazyModule(new NonBlockingDCache(cfg))
   }
 }
+
+/** Mix-ins for constructing tiles that have a HellaCache */
+trait HasHellaCache extends TileNetwork {
+  val module: HasHellaCacheModule
+  implicit val p: Parameters
+  def findScratchpadFromICache: Option[AddressSet]
+  var nDCachePorts = 0
+  val dcacheParams = p.alterPartial({ case CacheName => CacheName("L1D") })
+  val dcache = HellaCache(p(DCacheKey), findScratchpadFromICache _)(dcacheParams)
+  l1backend.node := dcache.node
+}
+
+trait HasHellaCacheBundle extends TileNetworkBundle {
+  val outer: HasHellaCache
+}
+
+trait HasHellaCacheModule extends TileNetworkModule {
+  val outer: HasHellaCache
+  //val io: HasHellaCacheBundle
+  val dcachePorts = ListBuffer[HellaCacheIO]()
+  val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.dcacheParams))
+  outer.dcache.module.io.cpu <> dcacheArb.io.mem
+}