Refactor Tile to use cake pattern (#502)

* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests

src/main/scala/rocket/Frontend.scala

@@ -5,8 +5,10 @@ package rocket
 
 import Chisel._
 import config._
+import coreplex._
 import diplomacy._
 import uncore.tilelink2._
+import uncore.util.CacheName
 import util._
 import Chisel.ImplicitConversions._
 
@@ -149,3 +151,23 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
   io.cpu.resp.bits.btb.valid := s2_btb_resp_valid
   io.cpu.resp.bits.btb.bits := s2_btb_resp_bits
 }
+
+/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
+trait HasICacheFrontend extends CanHavePTW with TileNetwork {
+  val module: HasICacheFrontendModule
+  val frontend = LazyModule(new Frontend()(p.alterPartial({
+    case CacheName => CacheName("L1I")
+  })))
+  l1backend.node := frontend.node
+  nPTWPorts += 1
+}
+
+trait HasICacheFrontendBundle extends TileNetworkBundle {
+  val outer: HasICacheFrontend
+}
+
+trait HasICacheFrontendModule extends CanHavePTWModule with TileNetworkModule {
+  val outer: HasICacheFrontend
+  //val io: HasICacheFrontendBundle
+  ptwPorts += outer.frontend.module.io.ptw
+}