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Refactor Tile to use cake pattern (#502)

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* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
2017-01-16 18:24:08 -08:00
committed by GitHub
parent 622e311962
commit 74b6a8d02b
32 changed files with 686 additions and 519 deletions
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4
src/main/scala/groundtest/Tile.scala
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@ -4,6 +4,7 @@
package groundtest
import Chisel._
import coreplex.BareTile
import rocket._
import uncore.tilelink._
import uncore.util.CacheName
@ -105,11 +106,10 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
class GroundTestTile(implicit p: Parameters) extends LazyModule with HasGroundTestParameters {
val dcacheParams = p.alterPartial {
case CacheName => CacheName("L1D")
case rocket.TLCacheEdge => cachedOut.edgesOut(0)
}
val slave = None
val dcache = HellaCache(p(DCacheKey))(dcacheParams)
val ucLegacy = LazyModule(new TLLegacy()(p))
val ucLegacy = LazyModule(new TLLegacy)
val cachedOut = TLOutputNode()
val uncachedOut = TLOutputNode()