Refactor Tile to use cake pattern (#502)

* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests

src/main/scala/groundtest/Configs.scala

@@ -13,7 +13,6 @@ import uncore.util._
 import uncore.devices.NTiles
 import junctions._
 import config._
-import scala.math.max
 import coreplex._
 import rocketchip._
 
@@ -74,24 +73,6 @@ class Edge32BitMemtestConfig extends Config(
 
 /* Composable Configs to set individual parameters */
 class WithGroundTest extends Config((site, here, up) => {
-  case TLKey("L1toL2") => {
-    val useMEI = site(NTiles) <= 1
-    val dataBeats = (8 * site(CacheBlockBytes)) / site(XLen)
-    TileLinkParameters(
-      coherencePolicy = (
-        if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
-        else new MESICoherence(site(L2DirectoryRepresentation))),
-      nManagers = site(BankedL2Config).nBanks + 1,
-      nCachingClients = 1,
-      nCachelessClients = 1,
-      maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
-                         site(GroundTestKey).map(_.maxXacts))
-                           .reduce(max(_, _)),
-      maxClientsPerPort = site(GroundTestKey).map(_.uncached).sum,
-      maxManagerXacts = site(NAcquireTransactors) + 2,
-      dataBeats = dataBeats,
-      dataBits = site(CacheBlockBytes)*8)
-  }
   case FPUKey => None
   case UseAtomics => false
   case UseCompressed => false

src/main/scala/groundtest/Coreplex.scala

@@ -6,19 +6,41 @@ import Chisel._
 import config._
 import diplomacy._
 import coreplex._
-import uncore.devices.NTiles
+import rocket._
+import uncore.agents._
+import uncore.coherence._
+import uncore.devices._
+import uncore.tilelink._
 import uncore.tilelink2._
-import uncore.tilelink.TLId
+import uncore.util._
+import scala.math.max
 
 case object TileId extends Field[Int]
 
 class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
   val tiles = List.tabulate(p(NTiles)) { i =>
-    LazyModule(new GroundTestTile()(p.alterPartial({
-      case TLId => "L1toL2"
+    LazyModule(new GroundTestTile()(p.alter { (site, here, up) => {
       case TileId => i
-    })))
+      case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
+      case AmoAluOperandBits => site(XLen)
+      case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
+      case TLId => "L1toL2"
+      case TLKey("L1toL2") =>
+        TileLinkParameters(
+          coherencePolicy = new MESICoherence(new NullRepresentation(site(NTiles))),
+          nManagers = site(BankedL2Config).nBanks + 1,
+          nCachingClients = 1,
+          nCachelessClients = 1,
+          maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
+                             site(GroundTestKey).map(_.maxXacts))
+                               .reduce(max(_, _)),
+          maxClientsPerPort = site(GroundTestKey).map(_.uncached).sum,
+          maxManagerXacts = 8,
+          dataBeats = (8 * site(CacheBlockBytes)) / site(XLen),
+          dataBits = site(CacheBlockBytes)*8)
+    }}))
   }
+
   tiles.foreach { lm =>
     l1tol2.node := lm.cachedOut
     l1tol2.node := lm.uncachedOut

src/main/scala/groundtest/Tile.scala

@@ -4,6 +4,7 @@
 package groundtest
 
 import Chisel._
+import coreplex.BareTile
 import rocket._
 import uncore.tilelink._
 import uncore.util.CacheName
@@ -105,11 +106,10 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
 class GroundTestTile(implicit p: Parameters) extends LazyModule with HasGroundTestParameters {
   val dcacheParams = p.alterPartial {
     case CacheName => CacheName("L1D")
-    case rocket.TLCacheEdge => cachedOut.edgesOut(0)
   }
   val slave = None
   val dcache = HellaCache(p(DCacheKey))(dcacheParams)
-  val ucLegacy = LazyModule(new TLLegacy()(p))
+  val ucLegacy = LazyModule(new TLLegacy)
 
    val cachedOut = TLOutputNode()
    val uncachedOut = TLOutputNode()

src/main/scala/groundtest/TraceGen.scala

@@ -23,7 +23,6 @@ import Chisel._
 import uncore.tilelink._
 import uncore.constants._
 import uncore.devices.NTiles
-import junctions._
 import rocket._
 import util.{Timer, DynamicTimer}
 import scala.util.Random