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Refactor Tile to use cake pattern (#502)

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* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
2017-01-16 18:24:08 -08:00
committed by GitHub
parent 622e311962
commit 74b6a8d02b
32 changed files with 686 additions and 519 deletions
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50
src/main/scala/coreplex/Coreplex.scala
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@ -4,69 +4,43 @@ package coreplex
import Chisel._
import config._
import junctions._
import diplomacy._
import uncore.tilelink._
import uncore.tilelink2._
import uncore.util._
import util._
import rocket._
/////
trait L2MasterPort extends CoreplexNetwork
{
val module: L2MasterPortModule
val l2in = TLInputNode()
l1tol2.node := l2in
}
trait L2MasterPortBundle extends CoreplexNetworkBundle
{
val outer: L2MasterPort
val l2in = outer.l2in.bundleIn
}
trait L2MasterPortModule extends CoreplexNetworkModule
{
val outer: L2MasterPort
val io: L2MasterPortBundle
}
/////
class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
with CoreplexRISCVPlatform
with L2MasterPort
with RocketTiles {
with HasL2MasterPort
with HasSynchronousRocketTiles {
override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
}
class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
with CoreplexRISCVPlatformBundle
with L2MasterPortBundle
with RocketTilesBundle
with HasL2MasterPortBundle
with HasSynchronousRocketTilesBundle
class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
with CoreplexRISCVPlatformModule
with L2MasterPortModule
with RocketTilesModule
with HasL2MasterPortModule
with HasSynchronousRocketTilesModule
/////
class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
with CoreplexRISCVPlatform
with L2MasterPort
with AsyncRocketTiles {
with HasL2MasterPort
with HasAsynchronousRocketTiles {
override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this))
}
class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
with CoreplexRISCVPlatformBundle
with L2MasterPortBundle
with AsyncRocketTilesBundle
with HasL2MasterPortBundle
with HasAsynchronousRocketTilesBundle
class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
with CoreplexRISCVPlatformModule
with L2MasterPortModule
with AsyncRocketTilesModule
with HasL2MasterPortModule
with HasAsynchronousRocketTilesModule