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Refactor Tile to use cake pattern (#502)

* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
2017-01-16 18:24:08 -08:00
committed by GitHub
parent 622e311962
commit 74b6a8d02b
32 changed files with 686 additions and 519 deletions

View File

@ -4,16 +4,10 @@ package coreplex
import Chisel._
import config._
import junctions._
import diplomacy._
import uncore.tilelink._
import rocket.{TileInterrupts, XLen}
import uncore.tilelink2._
import uncore.coherence._
import uncore.agents._
import uncore.devices._
import uncore.util._
import uncore.converters._
import rocket._
import util._
/** Widths of various points in the SoC */
@ -56,102 +50,17 @@ trait HasCoreplexParameters {
case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
abstract class BareCoreplex(implicit p: Parameters) extends LazyModule
abstract class BareCoreplexBundle[+L <: BareCoreplex](_outer: L) extends GenericParameterizedBundle(_outer) {
val outer = _outer
implicit val p = outer.p
}
abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
val outer = _outer
val io = _io ()
}
trait CoreplexNetwork extends HasCoreplexParameters {
val module: CoreplexNetworkModule
val l1tol2 = LazyModule(new TLXbar)
val l1tol2_beatBytes = l1tol2Config.beatBytes
val l1tol2_lineBytes = p(CacheBlockBytes)
val cbus = LazyModule(new TLXbar)
val cbus_beatBytes = cbusConfig.beatBytes
val cbus_lineBytes = l1tol2_lineBytes
val intBar = LazyModule(new IntXbar)
val mmio = TLOutputNode()
val mmioInt = IntInputNode()
intBar.intnode := mmioInt
cbus.node :=
TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
TLWidthWidget(l1tol2_beatBytes)(
TLBuffer()(
l1tol2.node)))
mmio :=
TLBuffer()(
TLWidthWidget(l1tol2_beatBytes)(
l1tol2.node))
}
trait CoreplexNetworkBundle extends HasCoreplexParameters {
val outer: CoreplexNetwork
val mmio = outer.mmio.bundleOut
val interrupts = outer.mmioInt.bundleIn
}
trait CoreplexNetworkModule extends HasCoreplexParameters {
val outer: CoreplexNetwork
val io: CoreplexNetworkBundle
println("\nGenerated Address Map")
for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) {
val prot = (if (manager.supportsGet) "R" else "") +
(if (manager.supportsPutFull) "W" else "") +
(if (manager.executable) "X" else "") +
(if (manager.supportsAcquire) " [C]" else "")
manager.address.foreach { a =>
println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot")
}
}
}
trait BankedL2CoherenceManagers extends CoreplexNetwork {
val module: BankedL2CoherenceManagersModule
require (isPow2(l2Config.nBanksPerChannel))
require (isPow2(l1tol2_lineBytes))
val mem = Seq.fill(l2Config.nMemoryChannels) {
val bankBar = LazyModule(new TLXbar)
val output = TLOutputNode()
output := bankBar.node
val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
for (i <- 0 until l2Config.nBanksPerChannel) {
val (in, out) = l2Config.coherenceManager(p)
in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node)
bankBar.node := out
}
output
}
}
trait BankedL2CoherenceManagersBundle extends CoreplexNetworkBundle {
val outer: BankedL2CoherenceManagers
require (l2Config.nMemoryChannels <= 1, "Seq in Chisel Bundle needed to support > 1") // !!!
val mem = outer.mem.map(_.bundleOut).toList.headOption // .headOption should be removed !!!
}
trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule {
val outer: BankedL2CoherenceManagers
val io: BankedL2CoherenceManagersBundle
}
abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
with CoreplexNetwork
with BankedL2CoherenceManagers {