riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add pf fault handling

Browse Source
This commit is contained in:
Yunsup Lee 2012-03-18 15:06:39 -07:00
parent 62ada5ea9e
commit 7493d55d3f
2 changed files with 11 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/cpu.scala
View File

@ -50,15 +50,15 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
vu.io.vec_tlb_resp.xcpt_ld := chosen_vec && dtlb.io.cpu_resp.xcpt_ld vu.io.vec_tlb_resp.xcpt_ld := chosen_vec && dtlb.io.cpu_resp.xcpt_ld
vu.io.vec_tlb_resp.xcpt_st := chosen_vec && dtlb.io.cpu_resp.xcpt_st vu.io.vec_tlb_resp.xcpt_st := chosen_vec && dtlb.io.cpu_resp.xcpt_st
vu.io.vec_tlb_resp.xcpt_pf := Bool(false)
vu.io.vec_tlb_resp.miss := chosen_vec && dtlb.io.cpu_resp.miss vu.io.vec_tlb_resp.miss := chosen_vec && dtlb.io.cpu_resp.miss
vu.io.vec_tlb_resp.ppn := dtlb.io.cpu_resp.ppn vu.io.vec_tlb_resp.ppn := dtlb.io.cpu_resp.ppn
// vector prefetch doesn't care about exceptions
// and shouldn't cause any anyways
dtlbarb.io.in(DTLB_VPF) <> vu.io.vec_pftlb_req dtlbarb.io.in(DTLB_VPF) <> vu.io.vec_pftlb_req
vu.io.vec_pftlb_resp.xcpt_ld := Bool(false) vu.io.vec_pftlb_resp.xcpt_ld := Bool(false)
vu.io.vec_pftlb_resp.xcpt_st := Bool(false) vu.io.vec_pftlb_resp.xcpt_st := Bool(false)
vu.io.vec_pftlb_resp.xcpt_pf := chosen_pf && dtlb.io.cpu_resp.xcpt_pf
vu.io.vec_pftlb_resp.miss := chosen_pf && dtlb.io.cpu_resp.miss vu.io.vec_pftlb_resp.miss := chosen_pf && dtlb.io.cpu_resp.miss
vu.io.vec_pftlb_resp.ppn := dtlb.io.cpu_resp.ppn vu.io.vec_pftlb_resp.ppn := dtlb.io.cpu_resp.ppn

23
rocket/src/main/scala/dtlb.scala
View File

@ -26,6 +26,7 @@ class ioDTLB_CPU_resp extends Bundle
val ppn = Bits(PPN_BITS, OUTPUT) val ppn = Bits(PPN_BITS, OUTPUT)
val xcpt_ld = Bool(OUTPUT) val xcpt_ld = Bool(OUTPUT)
val xcpt_st = Bool(OUTPUT) val xcpt_st = Bool(OUTPUT)
val xcpt_pf = Bool(OUTPUT)
} }
class ioDTLB extends Bundle class ioDTLB extends Bundle
@ -138,21 +139,15 @@ class rocketDTLB(entries: Int) extends Component
} }
} }
val access_fault_ld = val access_fault_common =
tlb_hit && (req_load || req_amo) && tlb_hit &&
((status_s && !sr_array(tag_hit_addr).toBool) || ((status_s && !sr_array(tag_hit_addr)) ||
(status_u && !ur_array(tag_hit_addr).toBool) || (status_u && !ur_array(tag_hit_addr)) ||
bad_va); bad_va)
io.cpu_resp.xcpt_ld := access_fault_ld; io.cpu_resp.xcpt_ld := access_fault_common && (req_load || req_amo)
io.cpu_resp.xcpt_st := access_fault_common && (req_store || req_amo)
val access_fault_st = io.cpu_resp.xcpt_pf := access_fault_common && req_pf
tlb_hit && (req_store || req_amo) &&
((status_s && !sw_array(tag_hit_addr).toBool) ||
(status_u && !uw_array(tag_hit_addr).toBool) ||
bad_va);
io.cpu_resp.xcpt_st := access_fault_st;
io.cpu_req.ready := (state === s_ready) && !tlb_miss; io.cpu_req.ready := (state === s_ready) && !tlb_miss;
io.cpu_resp.miss := tlb_miss; io.cpu_resp.miss := tlb_miss;