riscv/rocket-chip
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dcache loads working - 1/2 cycle load/use delay depending on load type

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This commit is contained in:
Rimas Avizienis 2011-11-01 22:04:45 -07:00
parent 3b3d988fde
commit 7479e085ec
3 changed files with 20 additions and 14 deletions
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17
rocket/src/main/scala/consts.scala
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@ -14,14 +14,15 @@ object Constants
val BR_J = UFix(7, 4); val BR_J = UFix(7, 4);
val BR_JR = UFix(8, 4); val BR_JR = UFix(8, 4);
val PC_4 = UFix(0, 3); val PC_4 = UFix(0, 4);
val PC_BTB = UFix(1, 3); val PC_BTB = UFix(1, 4);
val PC_EX4 = UFix(2, 3); val PC_EX4 = UFix(2, 4);
val PC_BR = UFix(3, 3); val PC_BR = UFix(3, 4);
val PC_J = UFix(4, 3); val PC_J = UFix(4, 4);
val PC_JR = UFix(5, 3); val PC_JR = UFix(5, 4);
val PC_PCR = UFix(6, 3); val PC_PCR = UFix(6, 4);
val PC_MEM = UFix(7, 3); val PC_MEM = UFix(7, 4);
val PC_MEM4 = UFix(8, 4);
val KF_Y = UFix(1, 1); val KF_Y = UFix(1, 1);
val KF_N = UFix(0, 1); val KF_N = UFix(0, 1);

13
rocket/src/main/scala/ctrl.scala
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@ -9,7 +9,7 @@ import Instructions._
class ioCtrlDpath extends Bundle() class ioCtrlDpath extends Bundle()
{ {
// outputs to datapath // outputs to datapath
val sel_pc = UFix(3, 'output); val sel_pc = UFix(4, 'output);
val wen_btb = Bool('output); val wen_btb = Bool('output);
val stallf = Bool('output); val stallf = Bool('output);
val stalld = Bool('output); val stalld = Bool('output);
@ -299,16 +299,19 @@ class rocketCtrl extends Component
mem_reg_mem_type <== ex_reg_mem_type; mem_reg_mem_type <== ex_reg_mem_type;
} }
// replay on a D$ load miss : FIXME - add a miss signal to D$ // replay PC when the D$ is blocked
val replay_mem_pc = mem_reg_mem_val && !io.dmem.req_rdy;
// replay PC+4 on a D$ load miss
val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD); val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
val replay_mem = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD) && !io.dmem.resp_val; val replay_mem_pc_plus4 = mem_cmd_load && !io.dmem.resp_val;
val dcache_miss = Reg(replay_mem); val dcache_miss = Reg(replay_mem_pc_plus4);
io.dpath.mem_load := mem_cmd_load; io.dpath.mem_load := mem_cmd_load;
io.dpath.dcache_miss := dcache_miss; io.dpath.dcache_miss := dcache_miss;
io.dpath.sel_pc := io.dpath.sel_pc :=
Mux(replay_mem, PC_MEM, Mux(replay_mem_pc, PC_MEM,
Mux(replay_mem_pc_plus4, PC_MEM4,
Mux(io.dpath.exception || ex_reg_eret, PC_PCR, Mux(io.dpath.exception || ex_reg_eret, PC_PCR,
Mux(!ex_reg_btb_hit && br_taken, PC_BR, Mux(!ex_reg_btb_hit && br_taken, PC_BR,
Mux(ex_reg_btb_hit && !br_taken || ex_reg_privileged, PC_EX4, Mux(ex_reg_btb_hit && !br_taken || ex_reg_privileged, PC_EX4,

4
rocket/src/main/scala/dpath.scala
View File

@ -130,7 +130,8 @@ class rocketDpath extends Component
Mux(io.ctrl.sel_pc === PC_J, ex_branch_target, Mux(io.ctrl.sel_pc === PC_J, ex_branch_target,
Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix, Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix,
Mux(io.ctrl.sel_pc === PC_PCR, ex_pcr(31,0).toUFix, Mux(io.ctrl.sel_pc === PC_PCR, ex_pcr(31,0).toUFix,
Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc_plus4, Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
Mux(io.ctrl.sel_pc === PC_MEM4, mem_reg_pc_plus4,
UFix(0, 32))))))))); UFix(0, 32)))))))));
when (!io.host.start){ when (!io.host.start){
@ -184,6 +185,7 @@ class rocketDpath extends Component
// moved this here to avoid having to do forward declaration // moved this here to avoid having to do forward declaration
// TODO: cleanup // TODO: cleanup
// 64/32 bit load handling (in mem stage)
val dmem_resp_pos = io.dmem.resp_tag(7,5).toUFix; val dmem_resp_pos = io.dmem.resp_tag(7,5).toUFix;
val dmem_resp_type = io.dmem.resp_tag(10,8); val dmem_resp_type = io.dmem.resp_tag(10,8);