riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Unbreak groundtest

Browse Source
This commit is contained in:
Andrew Waterman 2017-04-28 02:10:33 -07:00
parent 8fd5ecdff8
commit 7416f2a17e
2 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/HellaCache.scala
View File

@ -189,7 +189,7 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
implicit val p: Parameters
def findScratchpadFromICache: Option[AddressSet]
var nDCachePorts = 0
val dcache = HellaCache(usingBlockingDCache, findScratchpadFromICache _)
val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
masterNode := dcache.node
}

1
src/main/scala/tile/BaseTile.scala
View File

@ -32,7 +32,6 @@ trait HasTileParameters {
val usingRoCC = !tileParams.rocc.isEmpty
val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
val usingPTW = usingVM
val usingBlockingDCache = tileParams.dcache.get.nMSHRs == 0
val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
val hartIdLen = p(MaxHartIdBits)