From 7416f2a17e081dd0d065bde96b12dd3caa33778a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 28 Apr 2017 02:10:33 -0700 Subject: [PATCH] Unbreak groundtest --- src/main/scala/rocket/HellaCache.scala | 2 +- src/main/scala/tile/BaseTile.scala | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index c14cf0b4..70072321 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -189,7 +189,7 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters { implicit val p: Parameters def findScratchpadFromICache: Option[AddressSet] var nDCachePorts = 0 - val dcache = HellaCache(usingBlockingDCache, findScratchpadFromICache _) + val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _) masterNode := dcache.node } diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index ad10d2d6..3aef5be2 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -32,7 +32,6 @@ trait HasTileParameters { val usingRoCC = !tileParams.rocc.isEmpty val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0 val usingPTW = usingVM - val usingBlockingDCache = tileParams.dcache.get.nMSHRs == 0 val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined val hartIdLen = p(MaxHartIdBits)