riscv/rocket-chip
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Unbreak groundtest

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Andrew Waterman
2017-04-28 02:10:33 -07:00
parent 8fd5ecdff8
commit 7416f2a17e
2 changed files with 1 additions and 2 deletions
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src/main/scala/tile/BaseTile.scala
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@@ -32,7 +32,6 @@ trait HasTileParameters {
val usingRoCC = !tileParams.rocc.isEmpty
val usingBTB = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
val usingPTW = usingVM
val usingBlockingDCache = tileParams.dcache.get.nMSHRs == 0
val usingDataScratchpad = tileParams.dcache.flatMap(_.scratch).isDefined
val hartIdLen = p(MaxHartIdBits)