riscv/rocket-chip
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Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)

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This commit is contained in:
Yunsup Lee 2014-10-06 13:40:35 -07:00
parent f97a801d60
commit 73eac94a65
1 changed files with 113 additions and 105 deletions
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48
src/main/scala/PublicConfigs.scala
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@ -8,8 +8,11 @@ import rocket._
import rocket.Util._ import rocket.Util._
class DefaultConfig extends ChiselConfig { class DefaultConfig extends ChiselConfig {
type PF = PartialFunction[Any,Any]
val topDefinitions:World.TopDefs = { val topDefinitions:World.TopDefs = {
(pname,site,here) => pname match { (pname,site,here) => {
def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
pname match {
//RocketChip Parameters //RocketChip Parameters
case BuildTile => (r:Bool) => {new RocketTile(resetSignal = r)} case BuildTile => (r:Bool) => {new RocketTile(resetSignal = r)}
//HTIF Parameters //HTIF Parameters
@ -30,28 +33,32 @@ class DefaultConfig extends ChiselConfig {
case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits)) case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFDataBeats => site(TLDataBits)/site(MIFDataBits) case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
//Params used by all caches //Params used by all caches
case NSets => findBy(CacheName)
case NWays => findBy(CacheName)
case RowBits => findBy(CacheName)
case BlockOffBits => findBy(CacheName)
case ECCCode => None case ECCCode => None
case WordBits => site(XprLen) case WordBits => site(XprLen)
case Replacer => () => new RandomReplacement(site(NWays)) case Replacer => () => new RandomReplacement(site(NWays))
case BlockOffBits => site(CacheName) match { //Cache-Specific Params
case "L1I" | "L1D" => log2Up(site(TLDataBits)/8) case "L1I" => {
case "L2" => 0 case NSets => 128
} case NWays => 2
case NSets => site(CacheName) match { case RowBits => 4*site(CoreInstBits)
case "L1I" => 128 case BlockOffBits => log2Up(site(TLDataBits)/8)
case "L1D" => Knob("L1D_SETS") //128 }:PF
case "L2" => 512 case "L1D" => {
} case NSets => Knob("L1D_SETS") //128
case NWays => site(CacheName) match { case NWays => Knob("L1D_WAYS") //4
case "L1I" => 2 case RowBits => 2*site(CoreDataBits)
case "L1D" => Knob("L1D_WAYS") //4 case BlockOffBits => log2Up(site(TLDataBits)/8)
case "L2" => 8 }:PF
} case "L2" => {
case RowBits => site(CacheName) match { case NSets => 512
case "L1I" => 4*site(CoreInstBits) case NWays => 8
case "L1D" => 2*site(CoreDataBits) case RowBits => site(TLDataBits)
case "L2" => site(TLDataBits) case BlockOffBits => 0
} }:PF
//L1InstCache //L1InstCache
case NITLBEntries => 8 case NITLBEntries => 8
case NBTBEntries => 62 case NBTBEntries => 62
@ -117,6 +124,7 @@ class DefaultConfig extends ChiselConfig {
case Coherence => new MSICoherence(() => new NullRepresentation) case Coherence => new MSICoherence(() => new NullRepresentation)
} }
} }
}
override val knobValues:Any=>Any = { override val knobValues:Any=>Any = {
case "NTILES" => 1 case "NTILES" => 1
case "NBANKS" => 1 case "NBANKS" => 1