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diplomacy: use HeterogeneousBag instead of Vec

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This makes it possible for the bundles to have different widths.

Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities.  This would mean that if
you had two source[] fields, they end up the same.
This commit is contained in:
Wesley W. Terpstra
2017-02-22 17:05:22 -08:00
parent 027d6247b6
commit 735e4f8ed6
10 changed files with 29 additions and 34 deletions
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4
src/main/scala/uncore/axi4/Nodes.scala
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@ -12,8 +12,8 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters
def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
def bundleO(eo: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = Vec(eo.size, AXI4Bundle(AXI4BundleParameters.union(eo.map(_.bundle))))
def bundleI(ei: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = Vec(ei.size, AXI4Bundle(AXI4BundleParameters.union(ei.map(_.bundle))))
def bundleO(eo: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(eo.bundle)
def bundleI(ei: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(ei.bundle)
def colour = "#00ccff" // bluish
override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString

2
src/main/scala/uncore/axi4/RegisterRouter.scala
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@ -85,7 +85,7 @@ abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, conc
val intnode = uncore.tilelink2.IntSourceNode(interrupts)
}
case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])(implicit val p: Parameters)
case class AXI4RegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AXI4Bundle])(implicit val p: Parameters)
class AXI4RegBundleBase(arg: AXI4RegBundleArg) extends Bundle
{