From 735e4f8ed6a63ec5ce786f1711f9de91fd7283d8 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 22 Feb 2017 17:05:22 -0800 Subject: [PATCH] diplomacy: use HeterogeneousBag instead of Vec This makes it possible for the bundles to have different widths. Previously, we had to widen all the bundles passing through a node to the widest of all the possibilities. This would mean that if you had two source[] fields, they end up the same. --- src/main/scala/diplomacy/Nodes.scala | 21 ++++++++++--------- src/main/scala/uncore/ahb/Nodes.scala | 4 ++-- .../scala/uncore/ahb/RegisterRouter.scala | 2 +- src/main/scala/uncore/apb/Nodes.scala | 4 ++-- .../scala/uncore/apb/RegisterRouter.scala | 2 +- src/main/scala/uncore/axi4/Nodes.scala | 4 ++-- .../scala/uncore/axi4/RegisterRouter.scala | 2 +- .../scala/uncore/tilelink2/IntNodes.scala | 10 ++------- src/main/scala/uncore/tilelink2/Nodes.scala | 12 +++++------ .../uncore/tilelink2/RegisterRouter.scala | 2 +- 10 files changed, 29 insertions(+), 34 deletions(-) diff --git a/src/main/scala/diplomacy/Nodes.scala b/src/main/scala/diplomacy/Nodes.scala index 0796a367..312e9997 100644 --- a/src/main/scala/diplomacy/Nodes.scala +++ b/src/main/scala/diplomacy/Nodes.scala @@ -4,6 +4,7 @@ package diplomacy import Chisel._ import config._ +import util.HeterogeneousBag import scala.collection.mutable.ListBuffer import chisel3.internal.sourceinfo.SourceInfo @@ -14,7 +15,7 @@ import chisel3.internal.sourceinfo.SourceInfo trait InwardNodeImp[DI, UI, EI, BI <: Data] { def edgeI(pd: DI, pu: UI): EI - def bundleI(ei: Seq[EI]): Vec[BI] + def bundleI(ei: EI): BI def colour: String def connect(bindings: () => Seq[(EI, BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { (None, () => bindings().foreach { case (_, i, o) => i <> o }) @@ -33,7 +34,7 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data] trait OutwardNodeImp[DO, UO, EO, BO <: Data] { def edgeO(pd: DO, pu: UO): EO - def bundleO(eo: Seq[EO]): Vec[BO] + def bundleO(eo: EO): BO // optional methods to track node graph def mixO(pd: DO, node: OutwardNode[DO, UO, BO]): DO = pd // insert node into parameters @@ -112,7 +113,7 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI, protected[diplomacy] val iStar: Int protected[diplomacy] val iPortMapping: Seq[(Int, Int)] protected[diplomacy] val iParams: Seq[UI] - val bundleIn: Vec[BI] + val bundleIn: HeterogeneousBag[BI] } trait OutwardNodeHandle[DO, UO, BO <: Data] @@ -145,7 +146,7 @@ trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO protected[diplomacy] val oStar: Int protected[diplomacy] val oPortMapping: Seq[(Int, Int)] protected[diplomacy] val oParams: Seq[DO] - val bundleOut: Vec[BO] + val bundleOut: HeterogeneousBag[BO] } abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( @@ -218,14 +219,14 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( lazy val externalEdgesIn = if (externalIn) {edgesIn} else { Seq() } val flip = false // needed for blind nodes - private def flipO(b: Vec[BO]) = if (flip) b.flip else b - private def flipI(b: Vec[BI]) = if (flip) b else b.flip + private def flipO(b: HeterogeneousBag[BO]) = if (flip) b.flip else b + private def flipI(b: HeterogeneousBag[BI]) = if (flip) b else b.flip val wire = false // needed if you want to grab access to from inside a module - private def wireO(b: Vec[BO]) = if (wire) Wire(b) else b - private def wireI(b: Vec[BI]) = if (wire) Wire(b) else b + private def wireO(b: HeterogeneousBag[BO]) = if (wire) Wire(b) else b + private def wireI(b: HeterogeneousBag[BI]) = if (wire) Wire(b) else b - lazy val bundleOut = wireO(flipO(outer.bundleO(edgesOut))) - lazy val bundleIn = wireI(flipI(inner.bundleI(edgesIn))) + lazy val bundleOut = wireO(flipO(HeterogeneousBag(edgesOut.map(outer.bundleO(_))))) + lazy val bundleIn = wireI(flipI(HeterogeneousBag(edgesIn .map(inner.bundleI(_))))) // connects the outward part of a node with the inward part of this node private def bind(h: OutwardNodeHandle[DI, UI, BI], binding: NodeBinding)(implicit p: Parameters, sourceInfo: SourceInfo): Option[LazyModule] = { diff --git a/src/main/scala/uncore/ahb/Nodes.scala b/src/main/scala/uncore/ahb/Nodes.scala index 50843943..d50d62f9 100644 --- a/src/main/scala/uncore/ahb/Nodes.scala +++ b/src/main/scala/uncore/ahb/Nodes.scala @@ -12,8 +12,8 @@ object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, A def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu) def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu) - def bundleO(eo: Seq[AHBEdgeParameters]): Vec[AHBBundle] = Vec(eo.size, AHBBundle(AHBBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[AHBEdgeParameters]): Vec[AHBBundle] = Vec(ei.size, AHBBundle(AHBBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: AHBEdgeParameters): AHBBundle = AHBBundle(eo.bundle) + def bundleI(ei: AHBEdgeParameters): AHBBundle = AHBBundle(ei.bundle) def colour = "#00ccff" // bluish override def labelI(ei: AHBEdgeParameters) = (ei.slave.beatBytes * 8).toString diff --git a/src/main/scala/uncore/ahb/RegisterRouter.scala b/src/main/scala/uncore/ahb/RegisterRouter.scala index 034df6c8..e514292e 100644 --- a/src/main/scala/uncore/ahb/RegisterRouter.scala +++ b/src/main/scala/uncore/ahb/RegisterRouter.scala @@ -80,7 +80,7 @@ abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concu val intnode = uncore.tilelink2.IntSourceNode(interrupts) } -case class AHBRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AHBBundle])(implicit val p: Parameters) +case class AHBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AHBBundle])(implicit val p: Parameters) class AHBRegBundleBase(arg: AHBRegBundleArg) extends Bundle { diff --git a/src/main/scala/uncore/apb/Nodes.scala b/src/main/scala/uncore/apb/Nodes.scala index 999d23b2..c7d5fa7d 100644 --- a/src/main/scala/uncore/apb/Nodes.scala +++ b/src/main/scala/uncore/apb/Nodes.scala @@ -12,8 +12,8 @@ object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, A def edgeO(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu) def edgeI(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu) - def bundleO(eo: Seq[APBEdgeParameters]): Vec[APBBundle] = Vec(eo.size, APBBundle(APBBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[APBEdgeParameters]): Vec[APBBundle] = Vec(ei.size, APBBundle(APBBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: APBEdgeParameters): APBBundle = APBBundle(eo.bundle) + def bundleI(ei: APBEdgeParameters): APBBundle = APBBundle(ei.bundle) def colour = "#00ccff" // bluish override def labelI(ei: APBEdgeParameters) = (ei.slave.beatBytes * 8).toString diff --git a/src/main/scala/uncore/apb/RegisterRouter.scala b/src/main/scala/uncore/apb/RegisterRouter.scala index 2f8bfa86..62585d0e 100644 --- a/src/main/scala/uncore/apb/RegisterRouter.scala +++ b/src/main/scala/uncore/apb/RegisterRouter.scala @@ -64,7 +64,7 @@ abstract class APBRegisterRouterBase(address: AddressSet, interrupts: Int, concu val intnode = uncore.tilelink2.IntSourceNode(interrupts) } -case class APBRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[APBBundle])(implicit val p: Parameters) +case class APBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[APBBundle])(implicit val p: Parameters) class APBRegBundleBase(arg: APBRegBundleArg) extends Bundle { diff --git a/src/main/scala/uncore/axi4/Nodes.scala b/src/main/scala/uncore/axi4/Nodes.scala index fafe4c62..a4e1ca00 100644 --- a/src/main/scala/uncore/axi4/Nodes.scala +++ b/src/main/scala/uncore/axi4/Nodes.scala @@ -12,8 +12,8 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu) def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu) - def bundleO(eo: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = Vec(eo.size, AXI4Bundle(AXI4BundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = Vec(ei.size, AXI4Bundle(AXI4BundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(eo.bundle) + def bundleI(ei: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(ei.bundle) def colour = "#00ccff" // bluish override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString diff --git a/src/main/scala/uncore/axi4/RegisterRouter.scala b/src/main/scala/uncore/axi4/RegisterRouter.scala index 326f65eb..2da706bf 100644 --- a/src/main/scala/uncore/axi4/RegisterRouter.scala +++ b/src/main/scala/uncore/axi4/RegisterRouter.scala @@ -85,7 +85,7 @@ abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, conc val intnode = uncore.tilelink2.IntSourceNode(interrupts) } -case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])(implicit val p: Parameters) +case class AXI4RegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AXI4Bundle])(implicit val p: Parameters) class AXI4RegBundleBase(arg: AXI4RegBundleArg) extends Bundle { diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala index ddfa56e1..e83b3936 100644 --- a/src/main/scala/uncore/tilelink2/IntNodes.scala +++ b/src/main/scala/uncore/tilelink2/IntNodes.scala @@ -53,14 +53,8 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In { def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu) def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu) - def bundleO(eo: Seq[IntEdge]): Vec[Vec[Bool]] = { - if (eo.isEmpty) Vec(0, Vec(0, Bool())) else - Vec(eo.size, Vec(eo.map(_.source.num).max, Bool())) - } - def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = { - if (ei.isEmpty) Vec(0, Vec(0, Bool())) else - Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())) - } + def bundleO(eo: IntEdge): Vec[Bool] = Vec(eo.source.num, Bool()) + def bundleI(ei: IntEdge): Vec[Bool] = Vec(ei.source.num, Bool()) def colour = "#0000ff" // blue override def labelI(ei: IntEdge) = ei.source.sources.map(_.range.size).sum.toString diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala index 22701f12..23b50e01 100644 --- a/src/main/scala/uncore/tilelink2/Nodes.scala +++ b/src/main/scala/uncore/tilelink2/Nodes.scala @@ -18,8 +18,8 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu) def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(pd, pu) - def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = Vec(eo.size, TLBundle(TLBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = Vec(ei.size, TLBundle(TLBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: TLEdgeOut): TLBundle = TLBundle(eo.bundle) + def bundleI(ei: TLEdgeIn): TLBundle = TLBundle(ei.bundle) def colour = "#000000" // black override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString @@ -156,8 +156,8 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu) def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu) - def bundleO(eo: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = Vec(eo.size, new TLAsyncBundle(TLAsyncBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = Vec(ei.size, new TLAsyncBundle(TLAsyncBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(eo.bundle) + def bundleI(ei: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(ei.bundle) def colour = "#ff0000" // red override def labelI(ei: TLAsyncEdgeParameters) = ei.manager.depth.toString @@ -188,8 +188,8 @@ object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalM def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu) def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu) - def bundleO(eo: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(eo.size, new TLRationalBundle(TLBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(ei.size, new TLRationalBundle(TLBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(eo.bundle) + def bundleI(ei: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(ei.bundle) def colour = "#00ff00" // green diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index 2faa08dc..fc834c6d 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -86,7 +86,7 @@ abstract class TLRegisterRouterBase(val address: AddressSet, interrupts: Int, co val intnode = IntSourceNode(interrupts) } -case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])(implicit val p: Parameters) +case class TLRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[TLBundle])(implicit val p: Parameters) class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle {