more tlb/ptw debugging

rocket/src/main/scala/cpu.scala

@@ -62,13 +62,16 @@ class rocketProc extends Component
   itlb.io.cpu.status      := dpath.io.ctrl.status;
   itlb.io.cpu.req_val     := ctrl.io.imem.req_val;  
   itlb.io.cpu.req_asid    := Bits(0,ASID_BITS); // FIXME: connect to PCR
-  dtlb.io.cpu.req_vpn     := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
+  itlb.io.cpu.req_vpn     := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
-  io.imem.req_vpn         := itlb.io.cpu.resp_vpn;
+  io.imem.req_idx         := dpath.io.imem.req_addr(PGIDX_BITS-1,0);
+  io.imem.req_ppn         := itlb.io.cpu.resp_ppn;
+  io.imem.req_val         := ctrl.io.imem.req_val;
   ctrl.io.imem.req_rdy    := itlb.io.cpu.req_rdy && io.imem.req_rdy;  
   ctrl.io.imem.resp_val   := io.imem.resp_val;
   dpath.io.imem.resp_data := io.imem.resp_data;
   ctrl.io.xcpt_itlb       := itlb.io.cpu.exception;
   ctrl.io.itlb_miss       := itlb.io.cpu.resp_miss;
+  io.imem.itlb_miss       := itlb.io.cpu.resp_miss;
 
   
   // connect DTLB to D$ arbiter, ctrl+dpath

rocket/src/main/scala/dcache.scala

@@ -102,8 +102,6 @@ class rocketDCacheStoreGen extends Component {
   
 }
  
-
- 
 // state machine to flush (write back dirty lines, invalidate clean ones) the D$
 class rocketDCacheDM_flush(lines: Int) extends Component {
   val io = new ioDCacheDM();
@@ -212,7 +210,7 @@ class rocketDCacheDM(lines: Int) extends Component {
     r_cpu_req_tag   <== io.cpu.req_tag;
   }
   
-  when (state === s_ready) {
+  when ((state === s_ready) && r_cpu_req_val) {
     r_cpu_req_ppn <== io.cpu.req_ppn;
   }
   when (io.cpu.req_rdy) {
@@ -246,7 +244,7 @@ class rocketDCacheDM(lines: Int) extends Component {
   tag_array.io.d    := r_cpu_req_ppn;
   tag_array.io.we   := tag_we;
   tag_array.io.bweb := ~Bits(0,tagbits);
-  tag_array.io.ce   := Bool(true); // FIXME
+  tag_array.io.ce   := (state === s_ready) && io.cpu.req_val;
   val tag_rdata      = tag_array.io.q;
 
   // valid bit array
@@ -303,10 +301,7 @@ class rocketDCacheDM(lines: Int) extends Component {
   val store_data = Fill(2, storegen.io.store_data);
   val store_wmask_d = storegen.io.store_wmask;
   val store_idx_sel = p_store_idx(offsetlsb).toBool;
-  val store_wmask = 
+  val store_wmask = Mux(store_idx_sel, Cat(store_wmask_d, Bits(0,64)), Cat(Bits(0,64), store_wmask_d)); 
-    Mux(store_idx_sel, 
-  		Cat(store_wmask_d, Bits(0,64)),
-  		Cat(Bits(0,64), store_wmask_d)); 
 
   // data array
   val data_array = new rocketSRAMsp(lines*4, 128);
@@ -317,10 +312,7 @@ class rocketDCacheDM(lines: Int) extends Component {
     Mux((state === s_resolve_miss) || (state === s_replay_load),  r_cpu_req_idx(PGIDX_BITS-1, offsetmsb-1),
       io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1))))).toUFix;
       
-  data_array.io.d := 
+  data_array.io.d :=  Mux((state === s_refill), io.mem.resp_data, store_data);
-    Mux((state === s_refill), io.mem.resp_data, 
-    Mux((state === s_resolve_miss), Fill(2, p_store_data),
-      store_data));
   data_array.io.we := ((state === s_refill) && io.mem.resp_val) || drain_store || resolve_store;
   data_array.io.bweb := Mux((state === s_refill), ~Bits(0,128), store_wmask);
   data_array.io.ce := Bool(true); // FIXME

rocket/src/main/scala/icache.scala

@@ -8,9 +8,11 @@ import scala.math._;
 // interface between I$ and pipeline/ITLB (32 bits wide)
 class ioImem(view: List[String] = null) extends Bundle (view)
 {
-  val req_addr  = UFix(PADDR_BITS, 'input);
+  val itlb_miss  = Bool('input);
   val req_val   = Bool('input);
   val req_rdy   = Bool('output);
+  val req_idx   = Bits(PGIDX_BITS, 'input);
+  val req_ppn   = Bits(PPN_BITS, 'input);
   val resp_data = Bits(32, 'output);
   val resp_val  = Bool('output);
 }
@@ -45,8 +47,8 @@ class ioSRAMsp (width: Int, addrbits: Int) extends Bundle {
 class rocketSRAMsp(entries: Int, width: Int) extends Component {
   val addrbits = ceil(log10(entries)/log10(2)).toInt;
   val io = new ioSRAMsp(width, addrbits);
-  val sram = Mem(entries, io.we && io.ce, io.a, io.d, wrMask = io.bweb, resetVal = null);
+  val sram = Mem(entries, io.we, io.a, io.d, wrMask = io.bweb, resetVal = null);
-  val rdata = Reg(sram.read(io.a));
+  val rdata = Reg(Mux(io.ce, sram.read(io.a), Bits(0,width)));
   io.q := rdata;
 }
 
@@ -62,6 +64,7 @@ class rocketICacheDM(lines: Int) extends Component {
   val offsetbits = 6;
   val tagmsb    = addrbits - 1;
   val taglsb    = indexbits+offsetbits;
+  val tagbits   = addrbits-taglsb;
   val indexmsb  = taglsb-1;
   val indexlsb  = offsetbits;
   val offsetmsb = indexlsb-1;
@@ -71,49 +74,69 @@ class rocketICacheDM(lines: Int) extends Component {
   val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: s_resolve_miss :: Nil = Enum(6) { UFix() };
   val state = Reg(resetVal = s_reset);
   
-  val r_cpu_req_addr = Reg(Bits(0, addrbits));
+  val r_cpu_req_idx    = Reg(resetVal = Bits(0, PGIDX_BITS)); 
-  when (io.cpu.req_val && ((state === s_ready) || (state === s_resolve_miss))) {
+  val r_cpu_req_ppn    = Reg(resetVal = Bits(0, PPN_BITS)); 
-    r_cpu_req_addr <== io.cpu.req_addr;
+  val r_cpu_req_val    = Reg(resetVal = Bool(false));
-  }
   
-  val r_cpu_req_val = Reg(Bool(false));
+  when (io.cpu.req_val && io.cpu.req_rdy) {
-  when ((state === s_ready) || (state === s_resolve_miss)) {
+    r_cpu_req_idx   <== io.cpu.req_idx;
+  }
+  when (state === s_ready) {
+    r_cpu_req_ppn <== io.cpu.req_ppn;
+  }
+  when (io.cpu.req_rdy) {
     r_cpu_req_val <== io.cpu.req_val; 
   }
   otherwise {
     r_cpu_req_val <== Bool(false);
   }
   
+//   val r_cpu_req_addr = Reg(Bits(0, addrbits));
+//   when (io.cpu.req_val && ((state === s_ready) || (state === s_resolve_miss))) {
+//     r_cpu_req_addr <== io.cpu.req_addr;
+//   }
+  
+//   val r_cpu_req_val = Reg(Bool(false));
+//   when ((state === s_ready) || (state === s_resolve_miss)) {
+//     r_cpu_req_val <== io.cpu.req_val;
+//   }
+//   otherwise {
+//     r_cpu_req_val <== Bool(false);
+//   }
+
   val refill_count = Reg(resetVal = UFix(0,2));
   when (io.mem.resp_val) {
     refill_count <== refill_count + UFix(1);
   }
   
   // tag array
-  val tagbits = addrbits-(indexbits+offsetbits);
   val tag_array = new rocketSRAMsp(lines, tagbits);
-  tag_array.io.a := 
+  val tag_addr = 
-    Mux((state === s_refill_wait), r_cpu_req_addr(indexmsb, indexlsb).toUFix, io.cpu.req_addr(indexmsb, indexlsb));
+    Mux((state === s_refill_wait), r_cpu_req_idx(PGIDX_BITS-1,offsetbits),
-  tag_array.io.d    := r_cpu_req_addr(tagmsb, taglsb);
+      io.cpu.req_idx(PGIDX_BITS-1,offsetbits)).toUFix;
-  tag_array.io.we   := (state === s_refill_wait) && io.mem.resp_val;
+  val tag_we = (state === s_refill_wait) && io.mem.resp_val;
+  tag_array.io.a := tag_addr;
+  tag_array.io.d    := r_cpu_req_ppn;
+  tag_array.io.we   := tag_we;
   tag_array.io.bweb := ~Bits(0,tagbits);
-  tag_array.io.ce   := Bool(true); // FIXME
+  tag_array.io.ce   := (state === s_ready) && io.cpu.req_val;
-  val tag_lookup = tag_array.io.q;
+  val tag_rdata = tag_array.io.q;
   
   // valid bit array
   val vb_array = Reg(resetVal = Bits(0, lines));
-  val vb_rdata = Reg(vb_array(io.cpu.req_addr(indexmsb, indexlsb)));
+//   val vb_rdata = Reg(vb_array(io.cpu.req_addr(indexmsb, indexlsb)));
-  when ((state === s_refill_wait) && io.mem.resp_val) {
+  when (tag_we) {
-    vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(1,1));
+    vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
   }
 
-  val tag_match = vb_rdata.toBool && (tag_lookup === r_cpu_req_addr(tagmsb, taglsb));
+  val tag_valid = Reg(vb_array(tag_addr)).toBool;
+  val tag_match = (tag_rdata === io.cpu.req_ppn);
   
   // data array
   val data_array = new rocketSRAMsp(lines*4, 128);
   data_array.io.a := 
-    Mux((state === s_refill_wait) || (state === s_refill),  Cat(r_cpu_req_addr(indexmsb, indexlsb), refill_count),
+    Mux((state === s_refill_wait) || (state === s_refill),  Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count),
-      io.cpu.req_addr(indexmsb, offsetmsb-1)).toUFix;
+      io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
   data_array.io.d    := io.mem.resp_data;
   data_array.io.we   := io.mem.resp_val;
   data_array.io.bweb := ~Bits(0,128);
@@ -121,16 +144,17 @@ class rocketICacheDM(lines: Int) extends Component {
   val data_array_rdata = data_array.io.q;
    
   // output signals
-  io.cpu.resp_val := (r_cpu_req_val && tag_match && (state === s_ready)); //  || (state === s_resolve_miss);
+  io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_valid && tag_match; 
-  io.cpu.req_rdy  := ((state === s_ready) && (!r_cpu_req_val || (r_cpu_req_val && tag_match))); // || (state === s_resolve_miss);
+  io.cpu.req_rdy  := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || (tag_valid && tag_match));
   io.cpu.resp_data :=
-    MuxLookup(r_cpu_req_addr(offsetmsb-2, offsetlsb).toUFix, data_array_rdata(127, 96), 
+    MuxLookup(r_cpu_req_idx(offsetmsb-2, offsetlsb).toUFix, data_array_rdata(127, 96), 
       Array(UFix(2) -> data_array_rdata(95,64),
       UFix(1) -> data_array_rdata(63,32),
       UFix(0) -> data_array_rdata(31,0)));
 
   io.mem.req_val := (state === s_request);
-  io.mem.req_addr := Cat(r_cpu_req_addr(tagmsb, indexlsb), Bits(0,2)).toUFix;  
+  io.mem.req_addr := Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), Bits(0,2)).toUFix;
+  // Cat(r_cpu_req_addr(tagmsb, indexlsb), Bits(0,2)).toUFix;  
 
   // control state machine
   switch (state) {
@@ -138,17 +162,23 @@ class rocketICacheDM(lines: Int) extends Component {
       state <== s_ready;
     }
     is (s_ready) {
-      when (r_cpu_req_val && !tag_match) { state <== s_request; }
+      when (!io.cpu.itlb_miss && r_cpu_req_val && !(tag_valid && tag_match)) { state <== s_request; }
     }
     is (s_request)
     {
-      when (io.mem.req_rdy) { state <== s_refill_wait; }
+      when (io.mem.req_rdy) {
+        state <== s_refill_wait;
+      }
     }
     is (s_refill_wait) {
-      when (io.mem.resp_val)  { state <== s_refill; }
+      when (io.mem.resp_val) {
+        state <== s_refill;
+      }
     }
     is (s_refill) {
-      when (io.mem.resp_val && (refill_count === UFix(3,2))) { state <== s_resolve_miss; }
+      when (io.mem.resp_val && (refill_count === UFix(3,2))) {
+        state <== s_resolve_miss;
+      }
     }
     is (s_resolve_miss) {
       state <== s_ready;

rocket/src/main/scala/itlb.scala

@@ -97,7 +97,6 @@ class rocketITLB(entries: Int) extends Component
   
   val r_cpu_req_vpn     = Reg(resetVal = Bits(0, VPN_BITS));
   val r_cpu_req_val     = Reg(resetVal = Bool(false));
-  val r_cpu_req_cmd     = Reg(resetVal = Bits(0,4));
   val r_cpu_req_asid    = Reg(resetVal = Bits(0,ASID_BITS));
   val r_refill_tag   = Reg(resetVal = Bits(0, ASID_BITS+VPN_BITS));
   val r_refill_waddr = Reg(resetVal = UFix(0, addr_bits));
@@ -175,8 +174,8 @@ class rocketITLB(entries: Int) extends Component
     ((status_s && !sx_array(tag_hit_addr).toBool) ||
      (status_u && !ux_array(tag_hit_addr).toBool));
   
-  io.cpu.req_rdy   := (state === s_ready);
+  io.cpu.req_rdy   := Mux(status_vm, (state === s_ready) && (!r_cpu_req_val || tag_hit), Bool(true));
-  io.cpu.resp_miss := tlb_miss;
+  io.cpu.resp_miss := tlb_miss || (state != s_ready);
   io.cpu.resp_ppn := Mux(status_vm, tag_ram(tag_hit_addr), r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;
   
   io.ptw.req_val := (state === s_request);

rocket/src/main/scala/ptw.scala

@@ -16,11 +16,16 @@ class rocketDmemArbiter extends Component
 {
   val io = new ioDmemArbiter();
   
+  // must delay ppn part of address from PTW by 1 cycle (to match TLB behavior)
+  val r_ptw_req_val = Reg(io.ptw.req_val);
+  val r_ptw_req_ppn = Reg(io.ptw.req_ppn);
+  
   io.mem.req_val  := io.ptw.req_val || io.cpu.req_val;
   io.mem.req_cmd  := Mux(io.ptw.req_val, io.ptw.req_cmd,  io.cpu.req_cmd);
   io.mem.req_type := Mux(io.ptw.req_val, io.ptw.req_type, io.cpu.req_type);
   io.mem.req_idx  := Mux(io.ptw.req_val, io.ptw.req_idx, io.cpu.req_idx);
-  io.mem.req_ppn  := Mux(io.ptw.req_val, io.ptw.req_ppn, io.cpu.req_ppn);
+//   io.mem.req_ppn  := Mux(io.ptw.req_val, io.ptw.req_ppn, io.cpu.req_ppn);
+  io.mem.req_ppn  := Mux(r_ptw_req_val, r_ptw_req_ppn, io.cpu.req_ppn);
   io.mem.req_data := io.cpu.req_data;
   io.mem.req_tag  := Mux(io.ptw.req_val, Bits(0,5), io.cpu.req_tag);