riscv/rocket-chip
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more tlb/ptw debugging

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This commit is contained in:
Rimas Avizienis
2011-11-12 00:25:06 -08:00
parent 44926866b7
commit 73416f224b
5 changed files with 81 additions and 52 deletions
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7
rocket/src/main/scala/ptw.scala
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@ -16,11 +16,16 @@ class rocketDmemArbiter extends Component
{
val io = new ioDmemArbiter();
// must delay ppn part of address from PTW by 1 cycle (to match TLB behavior)
val r_ptw_req_val = Reg(io.ptw.req_val);
val r_ptw_req_ppn = Reg(io.ptw.req_ppn);
io.mem.req_val := io.ptw.req_val || io.cpu.req_val;
io.mem.req_cmd := Mux(io.ptw.req_val, io.ptw.req_cmd, io.cpu.req_cmd);
io.mem.req_type := Mux(io.ptw.req_val, io.ptw.req_type, io.cpu.req_type);
io.mem.req_idx := Mux(io.ptw.req_val, io.ptw.req_idx, io.cpu.req_idx);
io.mem.req_ppn := Mux(io.ptw.req_val, io.ptw.req_ppn, io.cpu.req_ppn);
// io.mem.req_ppn := Mux(io.ptw.req_val, io.ptw.req_ppn, io.cpu.req_ppn);
io.mem.req_ppn := Mux(r_ptw_req_val, r_ptw_req_ppn, io.cpu.req_ppn);
io.mem.req_data := io.cpu.req_data;
io.mem.req_tag := Mux(io.ptw.req_val, Bits(0,5), io.cpu.req_tag);