riscv/rocket-chip
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more tlb/ptw debugging

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This commit is contained in:
Rimas Avizienis
2011-11-12 00:25:06 -08:00
parent 44926866b7
commit 73416f224b
5 changed files with 81 additions and 52 deletions
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7
rocket/src/main/scala/cpu.scala
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@ -62,13 +62,16 @@ class rocketProc extends Component
itlb.io.cpu.status := dpath.io.ctrl.status;
itlb.io.cpu.req_val := ctrl.io.imem.req_val;
itlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
dtlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
io.imem.req_vpn := itlb.io.cpu.resp_vpn;
itlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
io.imem.req_idx := dpath.io.imem.req_addr(PGIDX_BITS-1,0);
io.imem.req_ppn := itlb.io.cpu.resp_ppn;
io.imem.req_val := ctrl.io.imem.req_val;
ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
ctrl.io.imem.resp_val := io.imem.resp_val;
dpath.io.imem.resp_data := io.imem.resp_data;
ctrl.io.xcpt_itlb := itlb.io.cpu.exception;
ctrl.io.itlb_miss := itlb.io.cpu.resp_miss;
io.imem.itlb_miss := itlb.io.cpu.resp_miss;
// connect DTLB to D$ arbiter, ctrl+dpath