riscv/rocket-chip
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AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample

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This commit is contained in:
Stephen Twigg 2013-09-24 16:32:49 -07:00
parent 81c752de84
commit 730a6ec76b
1 changed files with 8 additions and 3 deletions
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11
rocket/src/main/scala/rocc.scala
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@ -95,16 +95,21 @@ class AccumulatorExample(conf: RocketConfiguration) extends RoCC(conf)
cmd.ready := !stallReg && !stallLoad && !stallResp cmd.ready := !stallReg && !stallLoad && !stallResp
// command resolved if no stalls AND not issuing a load that will need a request // command resolved if no stalls AND not issuing a load that will need a request
// note, loadSent = true will occur when the load response comes back
// PROC RESPONSE INTERFACE
io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad
// valid response if valid command, need a response, and no stalls // valid response if valid command, need a response, and no stalls
io.resp.bits.rd := cmd.bits.inst.rd io.resp.bits.rd := cmd.bits.inst.rd
io.resp.bits.data := accum // Semantics is to always send out prior accumulator register value // Must respond with the appropriate tag or undefined behavior
io.resp.bits.data := accum
// Semantics is to always send out prior accumulator register value
io.busy := Bool(false) io.busy := cmd.valid || busy.reduce(_||_)
// Be busy when have pending memory requests or committed possibility of pending requests
io.interrupt := Bool(false) io.interrupt := Bool(false)
// Set this true to trigger an interrupt on the processor (please refer to supervisor documentation)
// MEMORY REQUEST INTERFACE
io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
io.mem.req.bits.addr := addend io.mem.req.bits.addr := addend
io.mem.req.bits.tag := addr io.mem.req.bits.tag := addr