riscv/rocket-chip
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No need to allow finishes to be sent in s_refill_resp state

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This is a hold-over from when writebacks needed finish messages.
This commit is contained in:
Andrew Waterman 2016-04-01 16:19:57 -07:00
parent 78bc18736e
commit 72f7f71eb5
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -342,7 +342,7 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val fq = Module(new FinishQueue(1)) val fq = Module(new FinishQueue(1))
val g = io.mem_grant.bits val g = io.mem_grant.bits
val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp val can_finish = state === s_invalid || state === s_refill_req
fq.io.enq.valid := io.mem_grant.valid && g.requiresAck() && refill_done fq.io.enq.valid := io.mem_grant.valid && g.requiresAck() && refill_done
fq.io.enq.bits := g.makeFinish() fq.io.enq.bits := g.makeFinish()
io.mem_finish.valid := fq.io.deq.valid && can_finish io.mem_finish.valid := fq.io.deq.valid && can_finish