riscv/rocket-chip
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broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle

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This commit is contained in:
Henry Cook 2013-05-01 10:05:54 -07:00
parent 1501e90c1f
commit 722bc917d3
1 changed files with 3 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -190,6 +190,7 @@ class MSHR(id: Int)(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfigura
val mem_finish = (new FIFOIO) { (new LogicalNetworkIO) {new GrantAck} } val mem_finish = (new FIFOIO) { (new LogicalNetworkIO) {new GrantAck} }
val wb_req = (new FIFOIO) { new WritebackReq } val wb_req = (new FIFOIO) { new WritebackReq }
val probe_rdy = Bool(OUTPUT) val probe_rdy = Bool(OUTPUT)
val mshr_rdy = Bool(INPUT)
} }
val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) { UFix() } val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) { UFix() }
@ -1012,7 +1013,8 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
// nack it like it's hot // nack it like it's hot
val s1_nack = dtlb.io.req.valid && dtlb.io.resp.miss || val s1_nack = dtlb.io.req.valid && dtlb.io.resp.miss ||
s1_req.addr(indexmsb,indexlsb) === prober.io.meta_write.bits.idx && !prober.io.req.ready s1_req.addr(indexmsb,indexlsb) === prober.io.meta_write.bits.idx && !prober.io.req.ready ||
s1_req.addr(tagmsb, indexlsb) === io.mem.probe.bits.payload.addr && io.mem.probe.fire()
val s2_nack_hit = RegEn(s1_nack, s1_valid || s1_replay) val s2_nack_hit = RegEn(s1_nack, s1_valid || s1_replay)
when (s2_nack_hit) { mshr.io.req.valid := Bool(false) } when (s2_nack_hit) { mshr.io.req.valid := Bool(false) }
val s2_nack_victim = s2_hit && mshr.io.secondary_miss val s2_nack_victim = s2_hit && mshr.io.secondary_miss