Merge pull request #675 from ucb-bar/debug_no_preexec

More Debug Updates to bring in line with spec

chisel3

@@ -1 +1 @@
-Subproject commit 00796dfce1ec3eba739467571cdfc52df2aa62de
+Subproject commit bb12fe7f61d12f51cf5d56b2a66aca0a1234abb3

regression/Makefile

@@ -216,19 +216,19 @@ stamps/%/emulator-torture-$(TORTURE_CONFIG).stamp: stamps/%/emulator-debug.stamp
 # Targets for JTAG DTM full-chain simulation
 
 #OPENOCD_HEAD ?= riscv
-OPENOCD_INSTALL ?= $(abspath $(TOP))/openocd-install
+OPENOCD_INSTALL ?= $(abspath $(TOP))/riscv-openocd-install
-#OPENOCD_VERSION = $(shell git ls-remote http://github.com/sifive/openocd.git $(OPENOCD_HEAD) | awk '{print $$1}')
+#OPENOCD_VERSION = $(shell git ls-remote git@github.com/riscv/riscv-openocd.git $(OPENOCD_HEAD) | awk '{print $$1}')
-OPENOCD_VERSION = 02c83d1ef348ce237b72e157fa6df6c4e791feb3
+OPENOCD_VERSION = 0e66b07550de9076620e45d1f90e38ac6ef8f9d1
 
 OPENOCD_DIR = $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/
 
 $(OPENOCD_DIR)/bin/openocd:
-	rm -rf openocd
+	rm -rf riscv-openocd
-	git clone http://github.com/sifive/openocd.git
+	git clone git@github.com:riscv/riscv-openocd.git
-	cd openocd ; \
+	cd riscv-openocd ; \
 	git checkout $(OPENOCD_VERSION) ; \
 	./bootstrap ; \
-	./configure --enable-jtag-vpi --prefix=$(OPENOCD_INSTALL)_$(OPENOCD_VERSION) ; \
+	./configure --enable-jtag-vpi --prefix=$(OPENOCD_INSTALL)_$(OPENOCD_VERSION) --disable-werror; \
 	make ; \
 	make install
 

riscv-tools

@@ -1 +1 @@
-Subproject commit cd8bc4798c38ba11118492474e96baf717c7af36
+Subproject commit 1bf2c200443a20291b4f35d565c54eb96dcdf40d

src/main/scala/rocket/CSR.scala

@@ -503,7 +503,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
   when (pending_interrupts.orR || exception) { reg_wfi := false }
   assert(!reg_wfi || io.retire === UInt(0))
 
-  when (io.retire(0)) { reg_singleStepped := true }
+  when (io.retire(0) || exception) { reg_singleStepped := true }
   when (!io.singleStep) { reg_singleStepped := false }
   assert(!io.singleStep || io.retire <= UInt(1))
   assert(!reg_singleStepped || io.retire === UInt(0))

src/main/scala/rocket/PMP.scala

@@ -80,7 +80,7 @@ class PMP(implicit p: Parameters) extends PMPReg {
     prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)
 
   private def pow2Homogeneous(x: UInt, pgLevel: UInt) = {
-    val maskHomogeneous = pgLevelMap { idxBits => mask(idxBits - 1) } (pgLevel)
+    val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel)
     maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0 } (pgLevel))
   }
 
@@ -92,7 +92,7 @@ class PMP(implicit p: Parameters) extends PMPReg {
     val beginsAfterLower = !(x < prev.comparand)
     val beginsAfterUpper = !(x < comparand)
 
-    val pgMask = pgLevelMap { idxBits => ((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)).U } (pgLevel)
+    val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel)
     val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)
     val endsBeforeUpper = (x & pgMask) < (comparand & pgMask)
 

src/main/scala/uncore/devices/debug/Debug.scala

@@ -52,19 +52,24 @@ object DsbRegAddrs{
   def RESUMING     = 0x108
   def EXCEPTION    = 0x10C
 
-  def FLAGS        = 0x400
-
-  def ROMBASE      = 0x800
-  def RESUME       = 0x804
-
   def WHERETO      = 0x300
-  def ABSTRACT     = 0x340 - 8
+  // This needs to be aligned for up to lq/sq
-  def PROGBUF      = 0x340
 
-  // This shows up in HartInfo
+  
+  // This shows up in HartInfo, and needs to be aligned
+  // to enable up to LQ/SQ instructions.
   def DATA         = 0x380
 
-  //Not implemented: Serial.
+  // We want DATA to immediately follow PROGBUF so that we can
+  // use them interchangeably.
+  def PROGBUF(cfg:DebugModuleConfig) = {DATA - (cfg.nProgramBufferWords * 4)}
+
+  // We want abstract to be immediately before PROGBUF
+  // because we auto-generate 2 instructions.
+  def ABSTRACT(cfg:DebugModuleConfig) = PROGBUF(cfg) - 8
+
+  def FLAGS        = 0x400
+  def ROMBASE      = 0x800
  
 }
 
@@ -226,8 +231,8 @@ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends Par
   *                      provide the default MTVEC since it is mapped
   *                      to address 0x0.
   *  
-  *  DebugModule is responsible for control registers and RAM. The Debug ROM is in a 
+  *  DebugModule is responsible for control registers and RAM, and
-  *  seperate module. It runs partially off of the dmiClk (e.g. TCK) and
+  *  Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and
   *  the TL clock. Therefore, it is divided into "Outer" portion (running
   *  of off dmiClock and dmiReset) and "Inner" (running off tlClock and tlReset).
   *  This allows DMCONTROL.haltreq, hartsel, dmactive, and ndreset to be
@@ -354,8 +359,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
       io.debugInterrupts(component)(0) := debugIntRegs(component)
     }
 
-    // Halt request registers are written by write to DMCONTROL.haltreq
+    // Halt request registers are set & cleared by writes to DMCONTROL.haltreq
-    // and cleared by writes to DMCONTROL.resumereq.
     // resumereq also causes the core to execute a 'dret',
     // so resumereq is passed through to Inner.
     // hartsel must also be used by the DebugModule state machine,
@@ -367,11 +371,8 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
       when (~dmactive) {
         debugIntNxt(component) := false.B
       }. otherwise {
-        when (DMCONTROLWrEn) {
+        when (DMCONTROLWrEn && DMCONTROLWrData.hartsel === component.U) {
-          when (DMCONTROLWrData.hartsel === component.U) {
+          debugIntNxt(component) := DMCONTROLWrData.haltreq
-            debugIntNxt(component) := (debugIntRegs(component) | DMCONTROLWrData.haltreq) &
-            ~(DMCONTROLWrData.resumereq)
-          }
         }
       }
     }
@@ -597,8 +598,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
       }.elsewhen (errorHaltResume) {
         ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U
       }.otherwise {
-        //TODO: Should be write-1-to-clear & ~ABSTRACTCSWrData.cmderr
+        when (ABSTRACTCSWrEn){
-        when (ABSTRACTCSWrEn /* && ABSTRACTCSWrData.cmderr === 0.U*/){
           ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr);
         }
       }
@@ -741,35 +741,15 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
     // "Variable" ROM Generation
     //--------------------------------------------------------------
 
-    val goProgramBuffer = Wire(init = false.B)
-    val goAbstract      = Wire(init = false.B)
-
-    val whereToReg = Reg(UInt(32.W))
-
-    val jalProgBuf  = Wire(init = (new GeneratedUJ()).fromBits(rocket.Instructions.JAL.value.U))
-    jalProgBuf.setImm(PROGBUF - WHERETO)
-    jalProgBuf.rd := 0.U
-
-    val jalAbstract  = Wire(init = (new GeneratedUJ()).fromBits(rocket.Instructions.JAL.value.U))
-    jalAbstract.setImm(ABSTRACT - WHERETO)
-    jalProgBuf.rd := 0.U
-
-    when (~io.dmactive) {
-      whereToReg := 0.U
-    }.otherwise{
-      when (goProgramBuffer) {
-        whereToReg := jalProgBuf.asUInt()
-      }.elsewhen (goAbstract) {
-        whereToReg := jalAbstract.asUInt()
-      }
-    }
-
     val goReg        = Reg(Bool())
+    val goAbstract   = Wire(init = false.B)
+    val jalAbstract  = Wire(init = (new GeneratedUJ()).fromBits(rocket.Instructions.JAL.value.U))
+    jalAbstract.setImm(ABSTRACT(cfg) - WHERETO)
 
     when (~io.dmactive){
       goReg := false.B
     }.otherwise {
-      when (goProgramBuffer | goAbstract) {
+      when (goAbstract) {
         goReg := true.B
       }.elsewhen (hartGoingWrEn){
         assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U)
@@ -864,7 +844,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
     nop.imm  := 0.U
 
     when (goAbstract) {
-      abstractGeneratedMem(0) := Mux(/*TODO: accessRegisterCommandReg.transfer*/true.B,
+      abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer,
         Mux(accessRegisterCommandReg.write,
           // To write a register, we need to do LW.
           abstractGeneratedI.asUInt(),
@@ -872,7 +852,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
           abstractGeneratedS.asUInt()),
         nop.asUInt()
       )
-      abstractGeneratedMem(1) := Mux(/*TODO accessRegisterCommandReg.postexec*/ false.B,
+      abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec,
         nop.asUInt(),
         rocket.Instructions.EBREAK.value.U)
     }
@@ -888,13 +868,14 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
       RESUMING    -> Seq(WNotify(sbIdWidth, hartResumingId,  hartResumingWrEn)),
       EXCEPTION   -> Seq(WNotify(sbIdWidth, hartExceptionId,  hartExceptionWrEn)),
       DATA        -> abstractDataMem.map(x => RegField(8, x)),
-      PROGBUF     -> programBufferMem.map(x => RegField(8, x)),
+      PROGBUF(cfg)-> programBufferMem.map(x => RegField(8, x)),
 
       // These sections are read-only.
-      ROMBASE     -> DebugRomContents().map(x => RegField.r(8, (x & 0xFF).U(8.W))),
+      WHERETO      -> Seq(RegField.r(32, jalAbstract.asUInt)),
+      ABSTRACT(cfg)-> abstractGeneratedMem.map{x => RegField.r(32, x)},
       FLAGS        -> flags.map{x => RegField.r(8, x.asUInt())},
-      WHERETO     -> Seq(RegField.r(32, whereToReg)),
+      ROMBASE      -> DebugRomContents().map(x => RegField.r(8, (x & 0xFF).U(8.W)))
-      ABSTRACT    -> abstractGeneratedMem.map(x => RegField.r(32, x))
+
     )
 
     // Override System Bus accesses with dmactive reset.
@@ -909,7 +890,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
 
     object CtrlState extends scala.Enumeration {
       type CtrlState = Value
-      val Waiting, CheckGenerate, PreExec, Abstract, PostExec = Value
+      val Waiting, CheckGenerate, Exec = Value
 
       def apply( t : Value) : UInt = {
         t.id.U(log2Up(values.size).W)
@@ -945,7 +926,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
     val commandRegIsUnsupported = Wire(init = true.B)
     val commandRegBadHaltResume = Wire(init = false.B)
     when (commandRegIsAccessRegister) {
-      when ((accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U)){
+      when (!accessRegisterCommandReg.transfer || (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U)){
         commandRegIsUnsupported := false.B
         commandRegBadHaltResume := ~hartHalted
       }
@@ -963,7 +944,6 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
       when (wrAccessRegisterCommand || regAccessRegisterCommand) {
         ctrlStateNxt := CtrlState(CheckGenerate)
       }
-
     }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){
 
       // We use this state to ensure that the COMMAND has been
@@ -977,47 +957,11 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
         errorHaltResume := true.B
         ctrlStateNxt := CtrlState(Waiting)
       }.otherwise {
-        when (accessRegisterCommandReg.preexec) {
+        ctrlStateNxt := CtrlState(Exec)
-          ctrlStateNxt    := CtrlState(PreExec)
-          goProgramBuffer := true.B
-        }.otherwise {
-          ctrlStateNxt := CtrlState(Abstract)
         goAbstract := true.B
       }
-      }
-    }.elsewhen (ctrlStateReg === CtrlState(PreExec)) {
     
-      // We can't just look at 'hartHalted' here, because
+    }.elsewhen (ctrlStateReg === CtrlState(Exec)) {
-      // hartHaltedWrEn is overloaded to mean 'got an ebreak'
-      // which may have happened when we were already halted.
-      when(goReg === false.B && hartHaltedWrEn && (cfg.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
-        ctrlStateNxt := CtrlState(Abstract)
-        goAbstract := true.B
-      }
-      when(hartExceptionWrEn) {
-        assert(hartExceptionId === 0.U,  "Unexpected 'EXCEPTION' hart")// Chisel3 #540, %x, expected %x", hartExceptionId, 0.U)
-        ctrlStateNxt := CtrlState(Waiting)
-        errorException := true.B
-      }
-    }.elsewhen (ctrlStateReg === CtrlState(Abstract)) {
-
-      // We can't just look at 'hartHalted' here, because
-      // hartHaltedWrEn is overloaded to mean 'got an ebreak'
-      // which may have happened when we were already halted.
-      when(goReg === false.B && hartHaltedWrEn && (cfg.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
-        when (accessRegisterCommandReg.postexec) {
-          ctrlStateNxt := CtrlState(PostExec)
-          goProgramBuffer := true.B
-        }.otherwise {
-          ctrlStateNxt := CtrlState(Waiting)
-        }
-      }
-      when(hartExceptionWrEn) {
-        assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540 %x, expected %x", hartExceptionId, selectedHartReg)
-        ctrlStateNxt := CtrlState(Waiting)
-        errorUnsupported := true.B
-      }
-    }.elsewhen (ctrlStateReg === CtrlState(PostExec)) {
 
       // We can't just look at 'hartHalted' here, because
       // hartHaltedWrEn is overloaded to mean 'got an ebreak'
@@ -1040,6 +984,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
   }
 }
 
+
 // Wrapper around TL Debug Module Inner and an Async DMI Sink interface.
 // Handles the synchronization of dmactive, which is used as a synchronous reset
 // inside the Inner block.

src/main/scala/uncore/devices/debug/abstract_commands.scala

@@ -28,8 +28,7 @@ class ACCESS_REGISTERFields extends Bundle {
   */
   val size = UInt(3.W)
 
-  // HACK -- for now I have not yet deleted preexecval reserved1 = UInt(1.W)
+  val reserved1 = UInt(1.W)
-  val preexec = Bool()
   
   /* When 1, execute the program in the Program Buffer exactly once
             after performing the transfer, if any.