riscv/rocket-chip
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add WidthAdapter from AXI slave to Coreplex TL slave

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Howard Mao 2016-09-27 12:07:02 -07:00 committed by Henry Cook
parent 7d6fb950b6
commit 71a9c78e4b
3 changed files with 8 additions and 6 deletions
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2
src/main/scala/groundtest/NastiTest.scala
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@ -115,7 +115,7 @@ class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p)
val test = Module(new NastiGenerator(genId)) val test = Module(new NastiGenerator(genId))
val converter = Module(new TileLinkIONastiIOConverter()( val converter = Module(new TileLinkIONastiIOConverter()(
p.alterPartial { case TLId => "MCtoEdge" })) p.alterPartial { case TLId => "EdgetoSlave" }))
converter.io.nasti <> test.io.mem converter.io.nasti <> test.io.mem
TileLinkWidthAdapter(io.mem.head, converter.io.tl) TileLinkWidthAdapter(io.mem.head, converter.io.tl)

2
src/main/scala/rocketchip/Configs.scala
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@ -39,6 +39,8 @@ class BasePlatformConfig extends Config(
addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)), addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
idBits = Dump("MEM_ID_BITS", site(MIFTagBits))) idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
} }
case TLKey("EdgetoSlave") =>
site(TLKey("L1toL2")).copy(dataBeats = site(MIFDataBeats))
case TLKey("MCtoEdge") => case TLKey("MCtoEdge") =>
site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats)) site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
case TLKey("MMIOtoEdge") => case TLKey("MMIOtoEdge") =>

10
src/main/scala/rocketchip/Periphery.scala
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@ -81,8 +81,8 @@ trait HasPeripheryParameters {
lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0 lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0
lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0 lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0 lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" }) lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
lazy val edgeSlaveParams = p.alterPartial({ case TLId => "EdgetoSlave" })
lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" }) lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" })
lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" }) lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" })
lazy val peripheryBusConfig = p(PeripheryBusKey) lazy val peripheryBusConfig = p(PeripheryBusKey)
@ -276,12 +276,12 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
else AsyncNastiFrom(io.bus_clk.get(idx), io.bus_rst.get(idx), bus) else AsyncNastiFrom(io.bus_clk.get(idx), io.bus_rst.get(idx), bus)
) )
} }
val conv = Module(new TileLinkIONastiIOConverter()(innerParams)) val conv = Module(new TileLinkIONastiIOConverter()(edgeSlaveParams))
conv.io.nasti <> arb.io.slave conv.io.nasti <> arb.io.slave
val r = outer.pBusMasters.range("ext") val (r_start, r_end) = outer.pBusMasters.range("ext")
require(r._2 - r._1 == 1, "RangeManager should return 1 slot") require(r_end - r_start == 1, "RangeManager should return 1 slot")
coreplexIO.slave(r._1) <> conv.io.tl TileLinkWidthAdapter(coreplexIO.slave(r_start), conv.io.tl)
} }
} }