From 71a9c78e4b9c3cbed615954811e02566ff21a561 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 27 Sep 2016 12:07:02 -0700 Subject: [PATCH] add WidthAdapter from AXI slave to Coreplex TL slave --- src/main/scala/groundtest/NastiTest.scala | 2 +- src/main/scala/rocketchip/Configs.scala | 2 ++ src/main/scala/rocketchip/Periphery.scala | 10 +++++----- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/main/scala/groundtest/NastiTest.scala b/src/main/scala/groundtest/NastiTest.scala index 656fe926..a769aa2d 100644 --- a/src/main/scala/groundtest/NastiTest.scala +++ b/src/main/scala/groundtest/NastiTest.scala @@ -115,7 +115,7 @@ class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p) val test = Module(new NastiGenerator(genId)) val converter = Module(new TileLinkIONastiIOConverter()( - p.alterPartial { case TLId => "MCtoEdge" })) + p.alterPartial { case TLId => "EdgetoSlave" })) converter.io.nasti <> test.io.mem TileLinkWidthAdapter(io.mem.head, converter.io.tl) diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala index 3f34c264..4dda1ee3 100644 --- a/src/main/scala/rocketchip/Configs.scala +++ b/src/main/scala/rocketchip/Configs.scala @@ -39,6 +39,8 @@ class BasePlatformConfig extends Config( addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)), idBits = Dump("MEM_ID_BITS", site(MIFTagBits))) } + case TLKey("EdgetoSlave") => + site(TLKey("L1toL2")).copy(dataBeats = site(MIFDataBeats)) case TLKey("MCtoEdge") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats)) case TLKey("MMIOtoEdge") => diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index 791e5571..47924e88 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -81,8 +81,8 @@ trait HasPeripheryParameters { lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0 lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0 lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0 - lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" }) lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" }) + lazy val edgeSlaveParams = p.alterPartial({ case TLId => "EdgetoSlave" }) lazy val edgeMemParams = p.alterPartial({ case TLId => "MCtoEdge" }) lazy val edgeMMIOParams = p.alterPartial({ case TLId => "MMIOtoEdge" }) lazy val peripheryBusConfig = p(PeripheryBusKey) @@ -276,12 +276,12 @@ trait PeripherySlaveModule extends HasPeripheryParameters { else AsyncNastiFrom(io.bus_clk.get(idx), io.bus_rst.get(idx), bus) ) } - val conv = Module(new TileLinkIONastiIOConverter()(innerParams)) + val conv = Module(new TileLinkIONastiIOConverter()(edgeSlaveParams)) conv.io.nasti <> arb.io.slave - val r = outer.pBusMasters.range("ext") - require(r._2 - r._1 == 1, "RangeManager should return 1 slot") - coreplexIO.slave(r._1) <> conv.io.tl + val (r_start, r_end) = outer.pBusMasters.range("ext") + require(r_end - r_start == 1, "RangeManager should return 1 slot") + TileLinkWidthAdapter(coreplexIO.slave(r_start), conv.io.tl) } }