WIP scala compile and firrtl elaborate; monitor error

2016-11-11 13:07:45 -08:00
parent afa1a6d549
commit 71315d5cf5
10 changed files with 136 additions and 158 deletions
--- a/src/main/scala/uncore/axi4/Parameters.scala
+++ b/src/main/scala/uncore/axi4/Parameters.scala
@ -8,7 +8,7 @@ import scala.math.max

 case class AXI4SlaveParameters(
  address:       Seq[AddressSet],
-  regionType:    RegionType.T  = RegionType.GET_EFFECTS,
+  regionType:    RegionType.T  = RegionType.UNCACHED,
  executable:    Boolean       = false, // processor can execute from this memory
  nodePath:      Seq[BaseNode] = Seq(),
  supportsWrite: TransferSizes = TransferSizes.none,