riscv/rocket-chip
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WIP scala compile and firrtl elaborate; monitor error

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This commit is contained in:
Henry Cook
2016-11-11 13:07:45 -08:00
parent afa1a6d549
commit 71315d5cf5
10 changed files with 136 additions and 158 deletions
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src/main/scala/rocket/rocket.scala
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@ -75,8 +75,6 @@ trait HasCoreParameters extends HasAddrMapParameters {
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
val nCustomMrwCsrs = p(NCustomMRWCSRs)
val nCores = p(NTiles)
val tileId = p(TileId)
// fetchWidth doubled, but coreInstBytes halved, for RVC
val decodeWidth = fetchWidth / (if (usingCompressed) 2 else 1)