riscv/rocket-chip
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WIP scala compile and firrtl elaborate; monitor error

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This commit is contained in:
Henry Cook
2016-11-11 13:07:45 -08:00
parent afa1a6d549
commit 71315d5cf5
10 changed files with 136 additions and 158 deletions
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5
src/main/scala/rocket/nbdcache.scala
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@ -73,14 +73,14 @@ trait HasMissInfo extends HasL1HellaCacheParameters {
val way_en = Bits(width = nWays)
}
class HellaCacheReqInternal(implicit p: Parameters) extends L1HellaCacheBundle()(p)
class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreMemOp {
val phys = Bool()
}
class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
class HellaCacheResp(implicit p: Parameters) extends L1HellaCacheBundle()(p)
class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreMemOp
with HasCoreData {
val replay = Bool()
@ -1245,6 +1245,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
object HellaCache {
def apply(cfg: DCacheConfig)(implicit p: Parameters) = LazyModule(new DCache)
// TODO convert non-blocking cache
// if (cfg.nMSHRs == 0) Module(new DCache()).io
// else Module(new HellaCache(cfg)).io
}